RISC-V integration
The integration should be similar to the POWERPC version.
Actually the syscall_intercept for RISC-V from Petar (https://github.com/Slate5/syscall_intercept) is forked to https://github.com/bsc-ssrg/syscall_intercept_riscv with some modifications needed to compile cleanly in licheepi
As a simple roadmap would be to :
Update dependencies so capstone > 5.0.0 is used when RISC-V version is selected ( I think that we could enable that update widely) , then clone the correct repository. (related issue to update #217 (closed) )
Inside the GekkoFS code, the syscall_no_intercept code needs to be changed.
All should be working on the LicheePi or similar available motherboard.
There is somework done in the RISCV branch.
Outcome: An integrated master, that allows installation on RISCV, (ARM, POWERPC) and Intel platforms without major issues.
