[MIPS] Fix pipeline hazard.

In the the sequence:
        ei
        ..
        mfc0    $x, $status

the mfc0 may not see the SR_IE bit set. This was a deliberate bug in the
kernel code because we knew this was a safe thing to do on all R2 silicon
so far but new silicon is changing this.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>