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Commit 5bc6e3cf authored by Graf Yang's avatar Graf Yang Committed by Mike Frysinger
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Blackfin: add CPLB entries for Core B on-chip L1 SRAM regions 



The Blackfin SMP port was missing CPLB entries for Core B on-chip L1 SRAM
regions.  Any code that attempted to use these would wrongly crash due to
a CPLB miss.

Signed-off-by: default avatarGraf Yang <graf.yang@analog.com>
Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent f574a76a
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