From c3a1c9c75b986e5a2c5d878ef0700a1ca6bb895a Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 26 Mar 2008 18:42:10 -0700 Subject: [PATCH 001/212] iop: Make IOP ATU window debug readable Make the inbound and outbound memory windows debugging meaningful to those who don't know what the register names for the ATU mean. IOW, use plain english rather than register jargon. Cc: Lennert Buytenhek Acked-by: Dan Williams Signed-off-by: Russell King --- arch/arm/plat-iop/pci.c | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index 98d01517b56..9e83066cc05 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c @@ -329,23 +329,28 @@ void __init iop3xx_pci_preinit(void) iop3xx_atu_setup(); } - DBG("PCI: Intel 803xx PCI init code.\n"); + DBG("PCI: Intel IOP3xx PCI init.\n"); + DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n", + *IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0); + DBG("PCI: Outbound memory window 1: PCI 0x%08x%08x\n", + *IOP3XX_OUMWTVR1, *IOP3XX_OMWTVR1); + DBG("PCI: Outbound IO window: PCI 0x%08x\n", + *IOP3XX_OIOWTVR); + + DBG("PCI: Inbound memory window 0: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", + *IOP3XX_IAUBAR0, *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0); + DBG("PCI: Inbound memory window 1: PCI 0x%08x%08x 0x%08x\n", + *IOP3XX_IAUBAR1, *IOP3XX_IABAR1, *IOP3XX_IALR1); + DBG("PCI: Inbound memory window 2: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", + *IOP3XX_IAUBAR2, *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2); + DBG("PCI: Inbound memory window 3: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", + *IOP3XX_IAUBAR3, *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3); + + DBG("PCI: Expansion ROM window: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", + 0, *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR); + DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD); - DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n", - *IOP3XX_OMWTVR0, - *IOP3XX_OIOWTVR); DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR); - DBG("ATU: IOP3XX_IABAR0=0x%08x IOP3XX_IALR0=0x%08x IOP3XX_IATVR0=%08x\n", - *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0); - DBG("ATU: IOP3XX_OMWTVR0=0x%08x\n", *IOP3XX_OMWTVR0); - DBG("ATU: IOP3XX_IABAR1=0x%08x IOP3XX_IALR1=0x%08x\n", - *IOP3XX_IABAR1, *IOP3XX_IALR1); - DBG("ATU: IOP3XX_ERBAR=0x%08x IOP3XX_ERLR=0x%08x IOP3XX_ERTVR=%08x\n", - *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR); - DBG("ATU: IOP3XX_IABAR2=0x%08x IOP3XX_IALR2=0x%08x IOP3XX_IATVR2=%08x\n", - *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2); - DBG("ATU: IOP3XX_IABAR3=0x%08x IOP3XX_IALR3=0x%08x IOP3XX_IATVR3=%08x\n", - *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3); hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort"); } -- GitLab From 27eedbf557f511efbe5651fa2fbfa0e4e8315ab7 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 26 Mar 2008 18:44:58 -0700 Subject: [PATCH 002/212] iop: when scanning PCI bus, translate the PCI addresses according to the outbound window settings ... otherwise we end up trying to access peripherals using wrong PCI addresses. Cc: Lennert Buytenhek Acked-by: Dan Williams Signed-off-by: Russell King --- arch/arm/plat-iop/pci.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index 9e83066cc05..ee6deaabf9b 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c @@ -209,8 +209,11 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys) res[1].flags = IORESOURCE_MEM; request_resource(&iomem_resource, &res[1]); - sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - IOP3XX_PCI_LOWER_MEM_BA; - sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - IOP3XX_PCI_LOWER_IO_BA; + /* + * Use whatever translation is already setup. + */ + sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0; + sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR; sys->resource[0] = &res[0]; sys->resource[1] = &res[1]; -- GitLab From 97c46048ce73c27fd2734299f07a8c06c8156a2e Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 26 Mar 2008 18:46:42 -0700 Subject: [PATCH 003/212] iop: Program outbound windows using the correct definitions The outbound translate registers should be programmed with the bus addresses that are defined in the header files, rather than the physical address. Currently it doesn't matter because they're identical, but the headers currently allow them to be different, and not using the right macros here means that people are in for a surprise if they change them. Cc: Lennert Buytenhek Acked-by: Dan Williams Signed-off-by: Russell King --- arch/arm/plat-iop/pci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index ee6deaabf9b..6ed374fa408 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c @@ -253,11 +253,11 @@ void __init iop3xx_atu_setup(void) *IOP3XX_IATVR2 = PHYS_OFFSET; /* Outbound window 0 */ - *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_PA; + *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_BA; *IOP3XX_OUMWTVR0 = 0; /* Outbound window 1 */ - *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE; + *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_BA + IOP3XX_PCI_MEM_WINDOW_SIZE; *IOP3XX_OUMWTVR1 = 0; /* BAR 3 ( Disabled ) */ @@ -268,7 +268,7 @@ void __init iop3xx_atu_setup(void) /* Setup the I/O Bar */ - *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_PA;; + *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_BA; /* Enable inbound and outbound cycles */ -- GitLab From c34002c102880bfac5b449b41e5313dcda186db8 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Wed, 26 Mar 2008 19:12:38 -0700 Subject: [PATCH 004/212] iop: unconditionally initialize the ATU on platforms known to be 'hosts' Platforms like iq80321 and iq80331 which may be host-bus-adapters require 'iop3xx_init_atu=y' to be specified on the kernel command line. Signed-off-by: Dan Williams --- arch/arm/mach-iop32x/Kconfig | 8 -------- arch/arm/mach-iop32x/iq31244.c | 11 ++++------- arch/arm/mach-iop32x/iq80321.c | 2 +- arch/arm/mach-iop33x/Kconfig | 8 -------- arch/arm/mach-iop33x/iq80331.c | 2 +- arch/arm/mach-iop33x/iq80332.c | 2 +- arch/arm/plat-iop/pci.c | 33 +++++++++++++++++++++++++------ include/asm-arm/hardware/iop3xx.h | 9 +-------- include/asm-arm/mach/pci.h | 1 + 9 files changed, 36 insertions(+), 40 deletions(-) diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig index dbe07c9472e..5e8c6f7dfab 100644 --- a/arch/arm/mach-iop32x/Kconfig +++ b/arch/arm/mach-iop32x/Kconfig @@ -34,14 +34,6 @@ config MACH_N2100 Say Y here if you want to run your kernel on the Thecus n2100 NAS appliance. -config IOP3XX_ATU - bool "Enable the PCI Controller" - default y - help - Say Y here if you want the IOP to initialize its PCI Controller. - Say N if the IOP is an add in card, the host system owns the PCI - bus in this case. - config MACH_EM7210 bool "Enable support for the Lanner EM7210" help diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c index 98cfa1cd6bd..4a89823bceb 100644 --- a/arch/arm/mach-iop32x/iq31244.c +++ b/arch/arm/mach-iop32x/iq31244.c @@ -178,10 +178,9 @@ static struct hw_pci iq31244_pci __initdata = { static int __init iq31244_pci_init(void) { - if (is_ep80219()) { - if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) - pci_common_init(&ep80219_pci); - } else if (machine_is_iq31244()) { + if (is_ep80219()) + pci_common_init(&ep80219_pci); + else if (machine_is_iq31244()) { if (is_80219()) { printk("note: iq31244 board type has been selected\n"); printk("note: to select ep80219 operation:\n"); @@ -190,9 +189,7 @@ static int __init iq31244_pci_init(void) printk("\t2/ update boot loader to pass" " the ep80219 id: %d\n", MACH_TYPE_EP80219); } - - if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) - pci_common_init(&iq31244_pci); + pci_common_init(&iq31244_pci); } return 0; diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c index 18ad29f213b..1da3c911edd 100644 --- a/arch/arm/mach-iop32x/iq80321.c +++ b/arch/arm/mach-iop32x/iq80321.c @@ -106,7 +106,7 @@ static struct hw_pci iq80321_pci __initdata = { .swizzle = pci_std_swizzle, .nr_controllers = 1, .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit, + .preinit = iop3xx_pci_preinit_cond, .scan = iop3xx_pci_scan_bus, .map_irq = iq80321_pci_map_irq, }; diff --git a/arch/arm/mach-iop33x/Kconfig b/arch/arm/mach-iop33x/Kconfig index 45598e09689..9aa016bb18f 100644 --- a/arch/arm/mach-iop33x/Kconfig +++ b/arch/arm/mach-iop33x/Kconfig @@ -16,14 +16,6 @@ config MACH_IQ80332 Say Y here if you want to run your kernel on the Intel IQ80332 evaluation kit for the IOP332 chipset. -config IOP3XX_ATU - bool "Enable the PCI Controller" - default y - help - Say Y here if you want the IOP to initialize its PCI Controller. - Say N if the IOP is an add in card, the host system owns the PCI - bus in this case. - endmenu endif diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c index 433188ebff2..de39fd77857 100644 --- a/arch/arm/mach-iop33x/iq80331.c +++ b/arch/arm/mach-iop33x/iq80331.c @@ -89,7 +89,7 @@ static struct hw_pci iq80331_pci __initdata = { .swizzle = pci_std_swizzle, .nr_controllers = 1, .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit, + .preinit = iop3xx_pci_preinit_cond, .scan = iop3xx_pci_scan_bus, .map_irq = iq80331_pci_map_irq, }; diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c index 416c09564cc..4904fd78445 100644 --- a/arch/arm/mach-iop33x/iq80332.c +++ b/arch/arm/mach-iop33x/iq80332.c @@ -89,7 +89,7 @@ static struct hw_pci iq80332_pci __initdata = { .swizzle = pci_std_swizzle, .nr_controllers = 1, .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit, + .preinit = iop3xx_pci_preinit_cond, .scan = iop3xx_pci_scan_bus, .map_irq = iq80332_pci_map_irq, }; diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c index 6ed374fa408..d9bc15a69e5 100644 --- a/arch/arm/plat-iop/pci.c +++ b/arch/arm/plat-iop/pci.c @@ -24,6 +24,7 @@ #include #include #include +#include // #define DEBUG @@ -325,13 +326,16 @@ void __init iop3xx_atu_disable(void) /* Flag to determine whether the ATU is initialized and the PCI bus scanned */ int init_atu; -void __init iop3xx_pci_preinit(void) -{ - if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) { - iop3xx_atu_disable(); - iop3xx_atu_setup(); - } +int iop3xx_get_init_atu(void) { + /* check if default has been overridden */ + if (init_atu != IOP3XX_INIT_ATU_DEFAULT) + return init_atu; + else + return IOP3XX_INIT_ATU_DISABLE; +} +static void __init iop3xx_atu_debug(void) +{ DBG("PCI: Intel IOP3xx PCI init.\n"); DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n", *IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0); @@ -358,6 +362,23 @@ void __init iop3xx_pci_preinit(void) hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort"); } +/* for platforms that might be host-bus-adapters */ +void __init iop3xx_pci_preinit_cond(void) +{ + if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) { + iop3xx_atu_disable(); + iop3xx_atu_setup(); + iop3xx_atu_debug(); + } +} + +void __init iop3xx_pci_preinit(void) +{ + iop3xx_atu_disable(); + iop3xx_atu_setup(); + iop3xx_atu_debug(); +} + /* allow init_atu to be user overridden */ static int __init iop3xx_init_atu_setup(char *str) { diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h index ede377ec914..18f6937f501 100644 --- a/include/asm-arm/hardware/iop3xx.h +++ b/include/asm-arm/hardware/iop3xx.h @@ -29,6 +29,7 @@ extern void gpio_line_config(int line, int direction); extern int gpio_line_get(int line); extern void gpio_line_set(int line, int value); extern int init_atu; +extern int iop3xx_get_init_atu(void); #endif @@ -112,14 +113,6 @@ extern int init_atu; #define IOP3XX_INIT_ATU_DISABLE -1 #define IOP3XX_INIT_ATU_ENABLE 1 -#ifdef CONFIG_IOP3XX_ATU -#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\ - IOP3XX_INIT_ATU_ENABLE : init_atu) -#else -#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\ - IOP3XX_INIT_ATU_DISABLE : init_atu) -#endif - /* Messaging Unit */ #define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310) #define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314) diff --git a/include/asm-arm/mach/pci.h b/include/asm-arm/mach/pci.h index 24621c49a0c..9d4f6b5ea41 100644 --- a/include/asm-arm/mach/pci.h +++ b/include/asm-arm/mach/pci.h @@ -55,6 +55,7 @@ void pci_common_init(struct hw_pci *); extern int iop3xx_pci_setup(int nr, struct pci_sys_data *); extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *); extern void iop3xx_pci_preinit(void); +extern void iop3xx_pci_preinit_cond(void); extern int dc21285_setup(int nr, struct pci_sys_data *); extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *); -- GitLab From abc848c182960118fbb7cdae397b5608c5bcef1b Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:39 -0400 Subject: [PATCH 005/212] introduce mbus DRAM target info abstraction Introduce struct mbus_dram_target_info, which will be used for passing information about the mbus target ID of the DDR unit, and mbus target attribute, base address and size for each of the DRAM chip selects from the platform code to peripheral drivers. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- include/linux/mbus.h | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 include/linux/mbus.h diff --git a/include/linux/mbus.h b/include/linux/mbus.h new file mode 100644 index 00000000000..c11ff293254 --- /dev/null +++ b/include/linux/mbus.h @@ -0,0 +1,36 @@ +/* + * Marvell MBUS common definitions. + * + * Copyright (C) 2008 Marvell Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __LINUX_MBUS_H +#define __LINUX_MBUS_H + +struct mbus_dram_target_info +{ + /* + * The 4-bit MBUS target ID of the DRAM controller. + */ + u8 mbus_dram_target_id; + + /* + * The base address, size, and MBUS attribute ID for each + * of the possible DRAM chip selects. Peripherals are + * required to support at least 4 decode windows. + */ + int num_cs; + struct mbus_dram_window { + u8 cs_index; + u8 mbus_attr; + u32 base; + u32 size; + } cs[4]; +}; + + +#endif -- GitLab From 83b6d822e4237052371e771b1f994823615a5341 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:39 -0400 Subject: [PATCH 006/212] Orion: initialise mbus DRAM target info on boot Initialise orion_mbus_dram_info on boot, and prepare for passing this info into peripheral drivers. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/addr-map.c | 29 +++++++++++++++++++++++++++++ arch/arm/mach-orion/common.c | 1 + arch/arm/mach-orion/common.h | 1 + 3 files changed, 31 insertions(+) diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c index 58cc3c0333b..ab4484cc14b 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion/addr-map.c @@ -12,6 +12,7 @@ #include #include +#include #include #include "common.h" @@ -168,6 +169,9 @@ #define SATA_WIN_BASE(win) ORION_SATA_REG(0x34 + ((win) * 0x10)) #define SATA_MAX_WIN 4 + +struct mbus_dram_target_info orion_mbus_dram_info; + static int __init orion_cpu_win_can_remap(u32 win) { u32 dev, rev; @@ -257,6 +261,7 @@ void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, in void __init orion_setup_cpu_wins(void) { int i; + int cs; /* * First, disable and clear windows @@ -281,6 +286,30 @@ void __init orion_setup_cpu_wins(void) ORION_PCIE_MEM_SIZE, -1); orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE, ORION_PCI_MEM_SIZE, -1); + + /* + * Setup MBUS dram target info. + */ + orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + + for (i = 0, cs = 0; i < 4; i++) { + u32 base = readl(DDR_BASE_CS(i)); + u32 size = readl(DDR_SIZE_CS(i)); + + /* + * Chip select enabled? + */ + if (size & 1) { + struct mbus_dram_window *w; + + w = &orion_mbus_dram_info.cs[cs++]; + w->cs_index = i; + w->mbus_attr = 0xf & ~(1 << i); + w->base = base & 0xff000000; + w->size = (size | 0x00ffffff) + 1; + } + } + orion_mbus_dram_info.num_cs = cs; } /* diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index bbc2b4ec932..cd9aa43bb47 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h index 501497cc2c4..2718245ec4a 100644 --- a/arch/arm/mach-orion/common.h +++ b/arch/arm/mach-orion/common.h @@ -29,6 +29,7 @@ enum orion_target { ORION_MAX_TARGETS }; +extern struct mbus_dram_target_info orion_mbus_dram_info; void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap); void orion_setup_cpu_wins(void); void orion_setup_eth_wins(void); -- GitLab From 1f2223b12b62a97d66e39199db50ed3fae9222c0 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:39 -0400 Subject: [PATCH 007/212] Orion: make PCIe/PCI support use mbus DRAM info Make the Orion PCIe/PCI code initialise MBUS decode windows based on mbus_dram_target_info instead of reading the info from the Orion DDR unit decode registers directly, and move the window code with the other PCI code, where it can be called as part of the generic PCIe/PCI init process. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/addr-map.c | 148 ---------------------------- arch/arm/mach-orion/common.c | 2 - arch/arm/mach-orion/common.h | 5 - arch/arm/mach-orion/pci.c | 171 ++++++++++++++++++++++++++++++++- 4 files changed, 168 insertions(+), 158 deletions(-) diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c index ab4484cc14b..69cd0876f6b 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion/addr-map.c @@ -92,56 +92,6 @@ #define CPU_WIN_DEV_CS1 6 #define CPU_WIN_DEV_CS2 7 -/* - * PCIE Address Decode Windows registers - */ -#define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4)) -#define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8)) -#define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8)) -#define PCIE_WIN_CTRL(n) (((n) < 5) ? \ - ORION_PCIE_REG(0x1820 + ((n) << 4)) : \ - ORION_PCIE_REG(0x1880)) -#define PCIE_WIN_BASE(n) (((n) < 5) ? \ - ORION_PCIE_REG(0x1824 + ((n) << 4)) : \ - ORION_PCIE_REG(0x1884)) -#define PCIE_WIN_REMAP(n) (((n) < 5) ? \ - ORION_PCIE_REG(0x182c + ((n) << 4)) : \ - ORION_PCIE_REG(0x188c)) -#define PCIE_DEFWIN_CTRL ORION_PCIE_REG(0x18b0) -#define PCIE_EXPROM_WIN_CTRL ORION_PCIE_REG(0x18c0) -#define PCIE_EXPROM_WIN_REMP ORION_PCIE_REG(0x18c4) -#define PCIE_MAX_BARS 3 -#define PCIE_MAX_WINS 6 - -/* - * Use PCIE BAR '1' for all DDR banks - */ -#define PCIE_DRAM_BAR 1 - -/* - * PCI Address Decode Windows registers - */ -#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \ - ((n) == 1) ? ORION_PCI_REG(0xd08) : \ - ((n) == 2) ? ORION_PCI_REG(0xc0c) : \ - ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0) -#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \ - ((n) == 1) ? ORION_PCI_REG(0xd48) : \ - ((n) == 2) ? ORION_PCI_REG(0xc4c) : \ - ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0) -#define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c) -#define PCI_CTRL_BASE_LO(n) ORION_PCI_REG(0x1e00 | ((n) << 4)) -#define PCI_CTRL_BASE_HI(n) ORION_PCI_REG(0x1e04 | ((n) << 4)) -#define PCI_CTRL_SIZE(n) ORION_PCI_REG(0x1e08 | ((n) << 4)) -#define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c) - -/* - * PCI configuration heleprs for BAR settings - */ -#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) -#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) -#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) - /* * Gigabit Ethernet Address Decode Windows registers */ @@ -312,104 +262,6 @@ void __init orion_setup_cpu_wins(void) orion_mbus_dram_info.num_cs = cs; } -/* - * Setup PCIE BARs and Address Decode Wins: - * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks - * WIN[0-3] -> DRAM bank[0-3] - */ -void __init orion_setup_pcie_wins(void) -{ - u32 base, size, i; - - /* - * First, disable and clear BARs and windows - */ - for (i = 1; i < PCIE_MAX_BARS; i++) { - orion_write(PCIE_BAR_CTRL(i), 0); - orion_write(PCIE_BAR_LO(i), 0); - orion_write(PCIE_BAR_HI(i), 0); - } - - for (i = 0; i < PCIE_MAX_WINS; i++) { - orion_write(PCIE_WIN_CTRL(i), 0); - orion_write(PCIE_WIN_BASE(i), 0); - orion_write(PCIE_WIN_REMAP(i), 0); - } - - /* - * Setup windows for DDR banks. Count total DDR size on the fly. - */ - base = DDR_REG_TO_BASE(orion_read(DDR_BASE_CS(0))); - size = 0; - for (i = 0; i < DDR_MAX_CS; i++) { - u32 bank_base, bank_size; - bank_size = orion_read(DDR_SIZE_CS(i)); - bank_base = orion_read(DDR_BASE_CS(i)); - if (bank_size & DDR_BANK_EN) { - bank_size = DDR_REG_TO_SIZE(bank_size); - bank_base = DDR_REG_TO_BASE(bank_base); - orion_write(PCIE_WIN_BASE(i), bank_base & 0xffff0000); - orion_write(PCIE_WIN_REMAP(i), 0); - orion_write(PCIE_WIN_CTRL(i), - ((bank_size-1) & 0xffff0000) | - (ATTR_DDR_CS(i) << 8) | - (TARGET_DDR << 4) | - (PCIE_DRAM_BAR << 1) | WIN_EN); - size += bank_size; - } - } - - /* - * Setup BAR[1] to all DRAM banks - */ - orion_write(PCIE_BAR_LO(PCIE_DRAM_BAR), base & 0xffff0000); - orion_write(PCIE_BAR_HI(PCIE_DRAM_BAR), 0); - orion_write(PCIE_BAR_CTRL(PCIE_DRAM_BAR), - ((size - 1) & 0xffff0000) | WIN_EN); -} - -void __init orion_setup_pci_wins(void) -{ - u32 base, size, i; - - /* - * First, disable windows - */ - orion_write(PCI_BAR_ENABLE, 0xffffffff); - - /* - * Setup windows for DDR banks. - */ - for (i = 0; i < DDR_MAX_CS; i++) { - base = orion_read(DDR_BASE_CS(i)); - size = orion_read(DDR_SIZE_CS(i)); - if (size & DDR_BANK_EN) { - u32 bus, dev, func, reg, val; - size = DDR_REG_TO_SIZE(size); - base = DDR_REG_TO_BASE(base); - bus = orion_pci_local_bus_nr(); - dev = orion_pci_local_dev_nr(); - func = PCI_CONF_FUNC_BAR_CS(i); - reg = PCI_CONF_REG_BAR_LO_CS(i); - orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val); - orion_pci_hw_wr_conf(bus, dev, func, reg, 4, - (base & 0xfffff000) | (val & 0xfff)); - reg = PCI_CONF_REG_BAR_HI_CS(i); - orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0); - orion_write(PCI_BAR_SIZE_DDR_CS(i), - (size - 1) & 0xfffff000); - orion_write(PCI_BAR_REMAP_DDR_CS(i), - base & 0xfffff000); - orion_clrbits(PCI_BAR_ENABLE, (1 << i)); - } - } - - /* - * Disable automatic update of address remaping when writing to BARs - */ - orion_setbits(PCI_ADDR_DECODE_CTRL, 1); -} - void __init orion_setup_usb_wins(void) { int i; diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index cd9aa43bb47..cc16588e8c0 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -336,8 +336,6 @@ void __init orion_init(void) orion_setup_cpu_wins(); orion_setup_usb_wins(); orion_setup_eth_wins(); - orion_setup_pci_wins(); - orion_setup_pcie_wins(); if (dev == MV88F5182_DEV_ID) orion_setup_sata_wins(); diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h index 2718245ec4a..961daaa0b91 100644 --- a/arch/arm/mach-orion/common.h +++ b/arch/arm/mach-orion/common.h @@ -34,8 +34,6 @@ void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap void orion_setup_cpu_wins(void); void orion_setup_eth_wins(void); void orion_setup_usb_wins(void); -void orion_setup_pci_wins(void); -void orion_setup_pcie_wins(void); void orion_setup_sata_wins(void); /* @@ -49,11 +47,8 @@ struct pci_bus; void orion_pcie_id(u32 *dev, u32 *rev); u32 orion_pcie_local_bus_nr(void); u32 orion_pci_local_bus_nr(void); -u32 orion_pci_local_dev_nr(void); int orion_pci_sys_setup(int nr, struct pci_sys_data *sys); struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); -int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 *val); -int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 val); /* * Valid GPIO pins according to MPP setup, used by machine-setup. diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c index b109bb46681..cfd3d064c20 100644 --- a/arch/arm/mach-orion/pci.c +++ b/arch/arm/mach-orion/pci.c @@ -12,6 +12,7 @@ #include #include +#include #include #include "common.h" @@ -58,6 +59,29 @@ #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) #define PCIE_CONF_ADDR_EN (1 << 31) +/* + * PCIE Address Decode Windows registers + */ +#define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4)) +#define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8)) +#define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8)) +#define PCIE_WIN_CTRL(n) (((n) < 5) ? \ + ORION_PCIE_REG(0x1820 + ((n) << 4)) : \ + ORION_PCIE_REG(0x1880)) +#define PCIE_WIN_BASE(n) (((n) < 5) ? \ + ORION_PCIE_REG(0x1824 + ((n) << 4)) : \ + ORION_PCIE_REG(0x1884)) +#define PCIE_WIN_REMAP(n) (((n) < 5) ? \ + ORION_PCIE_REG(0x182c + ((n) << 4)) : \ + ORION_PCIE_REG(0x188c)) +#define PCIE_MAX_BARS 3 +#define PCIE_MAX_WINS 6 + +/* + * Use PCIE BAR '1' for all DDR banks + */ +#define PCIE_DRAM_BAR 1 + /* * PCIE config cycles are done by programming the PCIE_CONF_ADDR register * and then reading the PCIE_CONF_DATA register. Need to make sure these @@ -95,6 +119,56 @@ static void orion_pcie_set_bus_nr(int nr) orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS); } +/* + * Setup PCIE BARs and Address Decode Wins: + * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks + * WIN[0-3] -> DRAM bank[0-3] + */ +static void orion_setup_pcie_wins(struct mbus_dram_target_info *dram) +{ + u32 size; + int i; + + /* + * First, disable and clear BARs and windows + */ + for (i = 1; i < PCIE_MAX_BARS; i++) { + writel(0, PCIE_BAR_CTRL(i)); + writel(0, PCIE_BAR_LO(i)); + writel(0, PCIE_BAR_HI(i)); + } + + for (i = 0; i < PCIE_MAX_WINS; i++) { + writel(0, PCIE_WIN_CTRL(i)); + writel(0, PCIE_WIN_BASE(i)); + writel(0, PCIE_WIN_REMAP(i)); + } + + /* + * Setup windows for DDR banks. Count total DDR size on the fly. + */ + size = 0; + for (i = 0; i < dram->num_cs; i++) { + struct mbus_dram_window *cs = dram->cs + i; + + writel(cs->base & 0xffff0000, PCIE_WIN_BASE(i)); + writel(0, PCIE_WIN_REMAP(i)); + writel(((cs->size - 1) & 0xffff0000) | + (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | + (PCIE_DRAM_BAR << 1) | 1, PCIE_WIN_CTRL(i)); + + size += cs->size; + } + + /* + * Setup BAR[1] to all DRAM banks + */ + writel(dram->cs[0].base, PCIE_BAR_LO(PCIE_DRAM_BAR)); + writel(0, PCIE_BAR_HI(PCIE_DRAM_BAR)); + writel(((size - 1) & 0xffff0000) | 1, PCIE_BAR_CTRL(PCIE_DRAM_BAR)); +} + static void orion_pcie_master_slave_enable(void) { orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER | @@ -219,6 +293,11 @@ static int orion_pcie_setup(struct pci_sys_data *sys) { struct resource *res; + /* + * Point PCIe unit MBUS decode windows to DRAM space. + */ + orion_setup_pcie_wins(&orion_mbus_dram_info); + /* * Master + Slave enable */ @@ -310,6 +389,27 @@ static int orion_pcie_setup(struct pci_sys_data *sys) #define PCIX_STAT_BUS_OFFS 8 #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) +/* + * PCI Address Decode Windows registers + */ +#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \ + ((n) == 1) ? ORION_PCI_REG(0xd08) : \ + ((n) == 2) ? ORION_PCI_REG(0xc0c) : \ + ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0) +#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \ + ((n) == 1) ? ORION_PCI_REG(0xd48) : \ + ((n) == 2) ? ORION_PCI_REG(0xc4c) : \ + ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0) +#define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c) +#define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c) + +/* + * PCI configuration helpers for BAR settings + */ +#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) +#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) +#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) + /* * PCI config cycles are done by programming the PCI_CONF_ADDR register * and then reading the PCI_CONF_DATA register. Need to make sure these @@ -323,13 +423,13 @@ u32 orion_pci_local_bus_nr(void) return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); } -u32 orion_pci_local_dev_nr(void) +static u32 orion_pci_local_dev_nr(void) { u32 conf = orion_read(PCI_P2P_CONF); return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS); } -int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, +static int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 *val) { unsigned long flags; @@ -351,7 +451,7 @@ int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, return PCIBIOS_SUCCESSFUL; } -int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, +static int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 val) { unsigned long flags; @@ -451,10 +551,75 @@ static void orion_pci_master_slave_enable(void) orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7); } +static void orion_setup_pci_wins(struct mbus_dram_target_info *dram) +{ + u32 win_enable; + u32 bus; + u32 dev; + int i; + + /* + * First, disable windows. + */ + win_enable = 0xffffffff; + orion_write(PCI_BAR_ENABLE, win_enable); + + /* + * Setup windows for DDR banks. + */ + bus = orion_pci_local_bus_nr(); + dev = orion_pci_local_dev_nr(); + + for (i = 0; i < dram->num_cs; i++) { + struct mbus_dram_window *cs = dram->cs + i; + u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); + u32 reg; + u32 val; + + /* + * Write DRAM bank base address register. + */ + reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); + orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val); + val = (cs->base & 0xfffff000) | (val & 0xfff); + orion_pci_hw_wr_conf(bus, dev, func, reg, 4, val); + + /* + * Write DRAM bank size register. + */ + reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); + orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0); + orion_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), + (cs->size - 1) & 0xfffff000); + orion_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), + cs->base & 0xfffff000); + + /* + * Enable decode window for this chip select. + */ + win_enable &= ~(1 << cs->cs_index); + } + + /* + * Re-enable decode windows. + */ + orion_write(PCI_BAR_ENABLE, win_enable); + + /* + * Disable automatic update of address remaping when writing to BARs. + */ + orion_setbits(PCI_ADDR_DECODE_CTRL, 1); +} + static int orion_pci_setup(struct pci_sys_data *sys) { struct resource *res; + /* + * Point PCI unit MBUS decode windows to DRAM space. + */ + orion_setup_pci_wins(&orion_mbus_dram_info); + /* * Master + Slave enable */ -- GitLab From 92aecfa95523384923b52c8ddaf948fc02a53e82 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:39 -0400 Subject: [PATCH 008/212] ehci-orion: mbus decode window support Make it possible to pass mbus_dram_target_info to the ehci-orion driver via the platform data, make the ehci-orion driver program the window registers based on this data if it is passed in, and make the Orion platform setup code use this method instead of programming the EHCI mbus window registers by hand. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/addr-map.c | 49 --------------------------- arch/arm/mach-orion/common.c | 8 ++++- arch/arm/mach-orion/common.h | 1 - drivers/usb/host/ehci-orion.c | 36 ++++++++++++++++++-- include/asm-arm/arch-orion/platform.h | 9 +++++ 5 files changed, 50 insertions(+), 53 deletions(-) diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c index 69cd0876f6b..40bcb986ab9 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion/addr-map.c @@ -103,15 +103,6 @@ #define ETH_MAX_WIN 6 #define ETH_MAX_REMAP_WIN 4 -/* - * USB Address Decode Windows registers - */ -#define USB_WIN_CTRL(i, w) ((i == 0) ? ORION_USB0_REG(0x320 + ((w) << 4)) \ - : ORION_USB1_REG(0x320 + ((w) << 4))) -#define USB_WIN_BASE(i, w) ((i == 0) ? ORION_USB0_REG(0x324 + ((w) << 4)) \ - : ORION_USB1_REG(0x324 + ((w) << 4))) -#define USB_MAX_WIN 4 - /* * SATA Address Decode Windows registers */ @@ -262,46 +253,6 @@ void __init orion_setup_cpu_wins(void) orion_mbus_dram_info.num_cs = cs; } -void __init orion_setup_usb_wins(void) -{ - int i; - u32 usb_if, dev, rev; - u32 max_usb_if = 1; - - orion_pcie_id(&dev, &rev); - if (dev == MV88F5182_DEV_ID) - max_usb_if = 2; - - for (usb_if = 0; usb_if < max_usb_if; usb_if++) { - /* - * First, disable and clear windows - */ - for (i = 0; i < USB_MAX_WIN; i++) { - orion_write(USB_WIN_BASE(usb_if, i), 0); - orion_write(USB_WIN_CTRL(usb_if, i), 0); - } - - /* - * Setup windows for DDR banks. - */ - for (i = 0; i < DDR_MAX_CS; i++) { - u32 base, size; - size = orion_read(DDR_SIZE_CS(i)); - base = orion_read(DDR_BASE_CS(i)); - if (size & DDR_BANK_EN) { - base = DDR_REG_TO_BASE(base); - size = DDR_REG_TO_SIZE(size); - orion_write(USB_WIN_CTRL(usb_if, i), - ((size-1) & 0xffff0000) | - (ATTR_DDR_CS(i) << 8) | - (TARGET_DDR << 4) | WIN_EN); - orion_write(USB_WIN_BASE(usb_if, i), - base & 0xffff0000); - } - } - } -} - void __init orion_setup_eth_wins(void) { int i; diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index cc16588e8c0..d33c01dfc3f 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "common.h" /***************************************************************************** @@ -149,6 +150,10 @@ static struct resource orion_ehci1_resources[] = { }, }; +static struct orion_ehci_data orion_ehci_data = { + .dram = &orion_mbus_dram_info, +}; + static u64 ehci_dmamask = 0xffffffffUL; static struct platform_device orion_ehci0 = { @@ -157,6 +162,7 @@ static struct platform_device orion_ehci0 = { .dev = { .dma_mask = &ehci_dmamask, .coherent_dma_mask = 0xffffffff, + .platform_data = &orion_ehci_data, }, .resource = orion_ehci0_resources, .num_resources = ARRAY_SIZE(orion_ehci0_resources), @@ -168,6 +174,7 @@ static struct platform_device orion_ehci1 = { .dev = { .dma_mask = &ehci_dmamask, .coherent_dma_mask = 0xffffffff, + .platform_data = &orion_ehci_data, }, .resource = orion_ehci1_resources, .num_resources = ARRAY_SIZE(orion_ehci1_resources), @@ -334,7 +341,6 @@ void __init orion_init(void) * Setup Orion address map */ orion_setup_cpu_wins(); - orion_setup_usb_wins(); orion_setup_eth_wins(); if (dev == MV88F5182_DEV_ID) orion_setup_sata_wins(); diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h index 961daaa0b91..c100355754f 100644 --- a/arch/arm/mach-orion/common.h +++ b/arch/arm/mach-orion/common.h @@ -33,7 +33,6 @@ extern struct mbus_dram_target_info orion_mbus_dram_info; void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap); void orion_setup_cpu_wins(void); void orion_setup_eth_wins(void); -void orion_setup_usb_wins(void); void orion_setup_sata_wins(void); /* diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c index e129981f139..0f0eb89c8cf 100644 --- a/drivers/usb/host/ehci-orion.c +++ b/drivers/usb/host/ehci-orion.c @@ -11,15 +11,19 @@ #include #include #include +#include #include +#include #define rdl(off) __raw_readl(hcd->regs + (off)) #define wrl(off, val) __raw_writel((val), hcd->regs + (off)) -#define USB_CAUSE 0x310 -#define USB_MASK 0x314 #define USB_CMD 0x140 #define USB_MODE 0x1a8 +#define USB_CAUSE 0x310 +#define USB_MASK 0x314 +#define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4)) +#define USB_WINDOW_BASE(i) (0x324 + ((i) << 4)) #define USB_IPG 0x360 #define USB_PHY_PWR_CTRL 0x400 #define USB_PHY_TX_CTRL 0x420 @@ -162,8 +166,30 @@ static const struct hc_driver ehci_orion_hc_driver = { .bus_resume = ehci_bus_resume, }; +static void __init +ehci_orion_conf_mbus_windows(struct usb_hcd *hcd, + struct mbus_dram_target_info *dram) +{ + int i; + + for (i = 0; i < 4; i++) { + wrl(USB_WINDOW_CTRL(i), 0); + wrl(USB_WINDOW_BASE(i), 0); + } + + for (i = 0; i < dram->num_cs; i++) { + struct mbus_dram_window *cs = dram->cs + i; + + wrl(USB_WINDOW_CTRL(i), ((cs->size - 1) & 0xffff0000) | + (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1); + wrl(USB_WINDOW_BASE(i), cs->base); + } +} + static int __init ehci_orion_drv_probe(struct platform_device *pdev) { + struct orion_ehci_data *pd = pdev->dev.platform_data; struct resource *res; struct usb_hcd *hcd; struct ehci_hcd *ehci; @@ -226,6 +252,12 @@ static int __init ehci_orion_drv_probe(struct platform_device *pdev) ehci->is_tdi_rh_tt = 1; ehci->sbrn = 0x20; + /* + * (Re-)program MBUS remapping windows if we are asked to. + */ + if (pd != NULL && pd->dram != NULL) + ehci_orion_conf_mbus_windows(hcd, pd->dram); + /* * setup Orion USB controller */ diff --git a/include/asm-arm/arch-orion/platform.h b/include/asm-arm/arch-orion/platform.h index 143c38e2fa0..0e33fe536ef 100644 --- a/include/asm-arm/arch-orion/platform.h +++ b/include/asm-arm/arch-orion/platform.h @@ -11,6 +11,14 @@ #ifndef __ASM_ARCH_PLATFORM_H__ #define __ASM_ARCH_PLATFORM_H__ +/* + * Orion EHCI platform driver data. + */ +struct orion_ehci_data { + struct mbus_dram_target_info *dram; +}; + + /* * Device bus NAND private data */ @@ -22,4 +30,5 @@ struct orion_nand_data { u8 width; /* buswidth */ }; + #endif -- GitLab From 15a32632d94011911497052a96cdbf3b905b325d Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:39 -0400 Subject: [PATCH 009/212] sata_mv: mbus decode window support Make it possible to pass mbus_dram_target_info to the sata_mv driver via the platform data, make the sata_mv driver program the window registers based on this data if it is passed in, and make the Orion platform setup code use this method instead of programming the SATA mbus window registers by hand. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/addr-map.c | 39 ---------------------------------- arch/arm/mach-orion/common.c | 4 ++-- arch/arm/mach-orion/common.h | 1 - drivers/ata/sata_mv.c | 31 +++++++++++++++++++++++++++ include/linux/ata_platform.h | 3 +++ 5 files changed, 36 insertions(+), 42 deletions(-) diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c index 40bcb986ab9..3de5de9ac65 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion/addr-map.c @@ -103,13 +103,6 @@ #define ETH_MAX_WIN 6 #define ETH_MAX_REMAP_WIN 4 -/* - * SATA Address Decode Windows registers - */ -#define SATA_WIN_CTRL(win) ORION_SATA_REG(0x30 + ((win) * 0x10)) -#define SATA_WIN_BASE(win) ORION_SATA_REG(0x34 + ((win) * 0x10)) -#define SATA_MAX_WIN 4 - struct mbus_dram_target_info orion_mbus_dram_info; @@ -288,35 +281,3 @@ void __init orion_setup_eth_wins(void) } } } - -void __init orion_setup_sata_wins(void) -{ - int i; - - /* - * First, disable and clear windows - */ - for (i = 0; i < SATA_MAX_WIN; i++) { - orion_write(SATA_WIN_BASE(i), 0); - orion_write(SATA_WIN_CTRL(i), 0); - } - - /* - * Setup windows for DDR banks. - */ - for (i = 0; i < DDR_MAX_CS; i++) { - u32 base, size; - size = orion_read(DDR_SIZE_CS(i)); - base = orion_read(DDR_BASE_CS(i)); - if (size & DDR_BANK_EN) { - base = DDR_REG_TO_BASE(base); - size = DDR_REG_TO_SIZE(size); - orion_write(SATA_WIN_CTRL(i), - ((size-1) & 0xffff0000) | - (ATTR_DDR_CS(i) << 8) | - (TARGET_DDR << 4) | WIN_EN); - orion_write(SATA_WIN_BASE(i), - base & 0xffff0000); - } - } -} diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index d33c01dfc3f..a32fe8e108b 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -289,6 +290,7 @@ static struct platform_device orion_sata = { void __init orion_sata_init(struct mv_sata_platform_data *sata_data) { + sata_data->dram = &orion_mbus_dram_info; orion_sata.dev.platform_data = sata_data; platform_device_register(&orion_sata); } @@ -342,8 +344,6 @@ void __init orion_init(void) */ orion_setup_cpu_wins(); orion_setup_eth_wins(); - if (dev == MV88F5182_DEV_ID) - orion_setup_sata_wins(); /* * REgister devices diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h index c100355754f..b676be0a4a8 100644 --- a/arch/arm/mach-orion/common.h +++ b/arch/arm/mach-orion/common.h @@ -33,7 +33,6 @@ extern struct mbus_dram_target_info orion_mbus_dram_info; void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap); void orion_setup_cpu_wins(void); void orion_setup_eth_wins(void); -void orion_setup_sata_wins(void); /* * Shared code used internally by other Orion core functions. diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index 6ebebde8454..83584b6e1ba 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -74,6 +74,7 @@ #include #include #include +#include #include #include #include @@ -352,6 +353,9 @@ enum { #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) #define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) +#define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) +#define WINDOW_BASE(i) (0x20034 + ((i) << 4)) + enum { /* DMA boundary 0xffff is required by the s/g splitting * we need on /length/ in mv_fill-sg(). @@ -2897,6 +2901,27 @@ static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) return 0; } +static void mv_conf_mbus_windows(struct mv_host_priv *hpriv, + struct mbus_dram_target_info *dram) +{ + int i; + + for (i = 0; i < 4; i++) { + writel(0, hpriv->base + WINDOW_CTRL(i)); + writel(0, hpriv->base + WINDOW_BASE(i)); + } + + for (i = 0; i < dram->num_cs; i++) { + struct mbus_dram_window *cs = dram->cs + i; + + writel(((cs->size - 1) & 0xffff0000) | + (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1, + hpriv->base + WINDOW_CTRL(i)); + writel(cs->base, hpriv->base + WINDOW_BASE(i)); + } +} + /** * mv_platform_probe - handle a positive probe of an soc Marvell * host @@ -2951,6 +2976,12 @@ static int mv_platform_probe(struct platform_device *pdev) res->end - res->start + 1); hpriv->base -= MV_SATAHC0_REG_BASE; + /* + * (Re-)program MBUS remapping windows if we are asked to. + */ + if (mv_platform_data->dram != NULL) + mv_conf_mbus_windows(hpriv, mv_platform_data->dram); + rc = mv_create_dma_pools(hpriv, &pdev->dev); if (rc) return rc; diff --git a/include/linux/ata_platform.h b/include/linux/ata_platform.h index b856a2a590d..9a26c83a2c9 100644 --- a/include/linux/ata_platform.h +++ b/include/linux/ata_platform.h @@ -27,7 +27,10 @@ extern int __devexit __pata_platform_remove(struct device *dev); /* * Marvell SATA private data */ +struct mbus_dram_target_info; + struct mv_sata_platform_data { + struct mbus_dram_target_info *dram; int n_ports; /* number of sata ports */ }; -- GitLab From 69b02f6a9639af89c099d06d5f2c4c66a1b03ebf Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:39 -0400 Subject: [PATCH 010/212] plat-orion: introduce Create arch/arm/plat-orion/, for peripherals shared between various Marvell Orion SoCs. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/Kconfig | 4 ++++ arch/arm/Makefile | 1 + arch/arm/plat-orion/Makefile | 8 ++++++++ 3 files changed, 13 insertions(+) create mode 100644 arch/arm/plat-orion/Makefile diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4039a133006..845f96e9f0d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -384,6 +384,7 @@ config ARCH_ORION select GENERIC_GPIO select GENERIC_TIME select GENERIC_CLOCKEVENTS + select PLAT_ORION help Support for Marvell Orion System on Chip family. @@ -563,6 +564,9 @@ config ARCH_ACORN config PLAT_IOP bool +config PLAT_ORION + bool + source arch/arm/mm/Kconfig config IWMMXT diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 1a4649667ec..27866cf0c18 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -185,6 +185,7 @@ core-$(CONFIG_VFP) += arch/arm/vfp/ # If we have a common platform directory, then include it in the build. core-$(CONFIG_PLAT_IOP) += arch/arm/plat-iop/ +core-$(CONFIG_PLAT_ORION) += arch/arm/plat-orion/ core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/ core-$(CONFIG_PLAT_S3C24XX) += arch/arm/plat-s3c24xx/ core-$(CONFIG_ARCH_MXC) += arch/arm/plat-mxc/ diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile new file mode 100644 index 00000000000..2327762133f --- /dev/null +++ b/arch/arm/plat-orion/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for the linux kernel. +# + +obj-y := +obj-m := +obj-n := +obj- := -- GitLab From 01eb569823792ab83b2810fcb31fa38560b08951 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:40 -0400 Subject: [PATCH 011/212] plat-orion: share IRQ handling code Split off Orion IRQ handling code into plat-orion/, and add support for multiple sets of (32) interrupts. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/irq.c | 35 +---------------- arch/arm/plat-orion/Makefile | 2 +- arch/arm/plat-orion/irq.c | 64 ++++++++++++++++++++++++++++++++ include/asm-arm/plat-orion/irq.h | 17 +++++++++ 4 files changed, 84 insertions(+), 34 deletions(-) create mode 100644 arch/arm/plat-orion/irq.c create mode 100644 include/asm-arm/plat-orion/irq.h diff --git a/arch/arm/mach-orion/irq.c b/arch/arm/mach-orion/irq.c index df7e12ad378..855793afcca 100644 --- a/arch/arm/mach-orion/irq.c +++ b/arch/arm/mach-orion/irq.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "common.h" /***************************************************************************** @@ -197,41 +198,9 @@ static void __init orion_init_gpio_irq(void) /***************************************************************************** * Orion Main IRQ ****************************************************************************/ -static void orion_main_irq_mask(u32 irq) -{ - orion_clrbits(MAIN_IRQ_MASK, 1 << irq); -} - -static void orion_main_irq_unmask(u32 irq) -{ - orion_setbits(MAIN_IRQ_MASK, 1 << irq); -} - -static struct irq_chip orion_main_irq_chip = { - .name = "Orion-IRQ-Main", - .ack = orion_main_irq_mask, - .mask = orion_main_irq_mask, - .unmask = orion_main_irq_unmask, -}; - static void __init orion_init_main_irq(void) { - int i; - - /* - * Mask and clear Main IRQ interrupts - */ - orion_write(MAIN_IRQ_MASK, 0x0); - orion_write(MAIN_IRQ_CAUSE, 0x0); - - /* - * Register level handler for Main IRQs - */ - for (i = 0; i < IRQ_ORION_GPIO_START; i++) { - set_irq_chip(i, &orion_main_irq_chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } + orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); } void __init orion_init_irq(void) diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile index 2327762133f..ea4ce342a19 100644 --- a/arch/arm/plat-orion/Makefile +++ b/arch/arm/plat-orion/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := +obj-y := irq.o obj-m := obj-n := obj- := diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c new file mode 100644 index 00000000000..c5b669d234b --- /dev/null +++ b/arch/arm/plat-orion/irq.c @@ -0,0 +1,64 @@ +/* + * arch/arm/plat-orion/irq.c + * + * Marvell Orion SoC IRQ handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +static void orion_irq_mask(u32 irq) +{ + void __iomem *maskaddr = get_irq_chip_data(irq); + u32 mask; + + mask = readl(maskaddr); + mask &= ~(1 << (irq & 31)); + writel(mask, maskaddr); +} + +static void orion_irq_unmask(u32 irq) +{ + void __iomem *maskaddr = get_irq_chip_data(irq); + u32 mask; + + mask = readl(maskaddr); + mask |= 1 << (irq & 31); + writel(mask, maskaddr); +} + +static struct irq_chip orion_irq_chip = { + .name = "orion_irq", + .ack = orion_irq_mask, + .mask = orion_irq_mask, + .unmask = orion_irq_unmask, +}; + +void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) +{ + unsigned int i; + + /* + * Mask all interrupts initially. + */ + writel(0, maskaddr); + + /* + * Register IRQ sources. + */ + for (i = 0; i < 32; i++) { + unsigned int irq = irq_start + i; + + set_irq_chip(irq, &orion_irq_chip); + set_irq_chip_data(irq, maskaddr); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } +} diff --git a/include/asm-arm/plat-orion/irq.h b/include/asm-arm/plat-orion/irq.h new file mode 100644 index 00000000000..94aeed919d5 --- /dev/null +++ b/include/asm-arm/plat-orion/irq.h @@ -0,0 +1,17 @@ +/* + * include/asm-arm/plat-orion/irq.h + * + * Marvell Orion SoC IRQ handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_PLAT_ORION_IRQ_H +#define __ASM_PLAT_ORION_IRQ_H + +void orion_irq_init(unsigned int irq_start, void __iomem *maskaddr); + + +#endif -- GitLab From abc0197d7a74e51a1581ce9971d7c2c0f2adadaf Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:40 -0400 Subject: [PATCH 012/212] plat-orion: share PCIe handling code Split off Orion PCIe handling code into plat-orion/. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/common.h | 4 +- arch/arm/mach-orion/pci.c | 343 ++++++++---------------------- arch/arm/plat-orion/Makefile | 2 +- arch/arm/plat-orion/pcie.c | 245 +++++++++++++++++++++ include/asm-arm/plat-orion/pcie.h | 31 +++ 5 files changed, 365 insertions(+), 260 deletions(-) create mode 100644 arch/arm/plat-orion/pcie.c create mode 100644 include/asm-arm/plat-orion/pcie.h diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h index b676be0a4a8..9a5afefac4d 100644 --- a/arch/arm/mach-orion/common.h +++ b/arch/arm/mach-orion/common.h @@ -43,8 +43,8 @@ struct pci_sys_data; struct pci_bus; void orion_pcie_id(u32 *dev, u32 *rev); -u32 orion_pcie_local_bus_nr(void); -u32 orion_pci_local_bus_nr(void); +int orion_pcie_local_bus_nr(void); +int orion_pci_local_bus_nr(void); int orion_pci_sys_setup(int nr, struct pci_sys_data *sys); struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c index cfd3d064c20..5240a245c7e 100644 --- a/arch/arm/mach-orion/pci.c +++ b/arch/arm/mach-orion/pci.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "common.h" /***************************************************************************** @@ -32,288 +33,136 @@ /***************************************************************************** * PCIE controller ****************************************************************************/ -#define PCIE_CTRL ORION_PCIE_REG(0x1a00) -#define PCIE_STAT ORION_PCIE_REG(0x1a04) -#define PCIE_DEV_ID ORION_PCIE_REG(0x0000) -#define PCIE_CMD_STAT ORION_PCIE_REG(0x0004) -#define PCIE_DEV_REV ORION_PCIE_REG(0x0008) -#define PCIE_MASK ORION_PCIE_REG(0x1910) -#define PCIE_CONF_ADDR ORION_PCIE_REG(0x18f8) -#define PCIE_CONF_DATA ORION_PCIE_REG(0x18fc) - -/* - * PCIE_STAT bits - */ -#define PCIE_STAT_LINK_DOWN 1 -#define PCIE_STAT_BUS_OFFS 8 -#define PCIE_STAT_BUS_MASK (0xff << PCIE_STAT_BUS_OFFS) -#define PCIE_STAT_DEV_OFFS 20 -#define PCIE_STAT_DEV_MASK (0x1f << PCIE_STAT_DEV_OFFS) - -/* - * PCIE_CONF_ADDR bits - */ -#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 24) | ((r) & 0xfc)) -#define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8) -#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) -#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) -#define PCIE_CONF_ADDR_EN (1 << 31) - -/* - * PCIE Address Decode Windows registers - */ -#define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4)) -#define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8)) -#define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8)) -#define PCIE_WIN_CTRL(n) (((n) < 5) ? \ - ORION_PCIE_REG(0x1820 + ((n) << 4)) : \ - ORION_PCIE_REG(0x1880)) -#define PCIE_WIN_BASE(n) (((n) < 5) ? \ - ORION_PCIE_REG(0x1824 + ((n) << 4)) : \ - ORION_PCIE_REG(0x1884)) -#define PCIE_WIN_REMAP(n) (((n) < 5) ? \ - ORION_PCIE_REG(0x182c + ((n) << 4)) : \ - ORION_PCIE_REG(0x188c)) -#define PCIE_MAX_BARS 3 -#define PCIE_MAX_WINS 6 - -/* - * Use PCIE BAR '1' for all DDR banks - */ -#define PCIE_DRAM_BAR 1 - -/* - * PCIE config cycles are done by programming the PCIE_CONF_ADDR register - * and then reading the PCIE_CONF_DATA register. Need to make sure these - * transactions are atomic. - */ -static DEFINE_SPINLOCK(orion_pcie_lock); +#define PCIE_BASE ((void __iomem *)ORION_PCIE_VIRT_BASE) void orion_pcie_id(u32 *dev, u32 *rev) { - *dev = orion_read(PCIE_DEV_ID) >> 16; - *rev = orion_read(PCIE_DEV_REV) & 0xff; -} - -u32 orion_pcie_local_bus_nr(void) -{ - u32 stat = orion_read(PCIE_STAT); - return((stat & PCIE_STAT_BUS_MASK) >> PCIE_STAT_BUS_OFFS); -} - -static u32 orion_pcie_local_dev_nr(void) -{ - u32 stat = orion_read(PCIE_STAT); - return((stat & PCIE_STAT_DEV_MASK) >> PCIE_STAT_DEV_OFFS); -} - -static u32 orion_pcie_no_link(void) -{ - u32 stat = orion_read(PCIE_STAT); - return(stat & PCIE_STAT_LINK_DOWN); -} - -static void orion_pcie_set_bus_nr(int nr) -{ - orion_clrbits(PCIE_STAT, PCIE_STAT_BUS_MASK); - orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS); + *dev = orion_pcie_dev_id(PCIE_BASE); + *rev = orion_pcie_rev(PCIE_BASE); } -/* - * Setup PCIE BARs and Address Decode Wins: - * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks - * WIN[0-3] -> DRAM bank[0-3] - */ -static void orion_setup_pcie_wins(struct mbus_dram_target_info *dram) +int orion_pcie_local_bus_nr(void) { - u32 size; - int i; - - /* - * First, disable and clear BARs and windows - */ - for (i = 1; i < PCIE_MAX_BARS; i++) { - writel(0, PCIE_BAR_CTRL(i)); - writel(0, PCIE_BAR_LO(i)); - writel(0, PCIE_BAR_HI(i)); - } - - for (i = 0; i < PCIE_MAX_WINS; i++) { - writel(0, PCIE_WIN_CTRL(i)); - writel(0, PCIE_WIN_BASE(i)); - writel(0, PCIE_WIN_REMAP(i)); - } - - /* - * Setup windows for DDR banks. Count total DDR size on the fly. - */ - size = 0; - for (i = 0; i < dram->num_cs; i++) { - struct mbus_dram_window *cs = dram->cs + i; - - writel(cs->base & 0xffff0000, PCIE_WIN_BASE(i)); - writel(0, PCIE_WIN_REMAP(i)); - writel(((cs->size - 1) & 0xffff0000) | - (cs->mbus_attr << 8) | - (dram->mbus_dram_target_id << 4) | - (PCIE_DRAM_BAR << 1) | 1, PCIE_WIN_CTRL(i)); - - size += cs->size; - } - - /* - * Setup BAR[1] to all DRAM banks - */ - writel(dram->cs[0].base, PCIE_BAR_LO(PCIE_DRAM_BAR)); - writel(0, PCIE_BAR_HI(PCIE_DRAM_BAR)); - writel(((size - 1) & 0xffff0000) | 1, PCIE_BAR_CTRL(PCIE_DRAM_BAR)); + return orion_pcie_get_local_bus_nr(PCIE_BASE); } -static void orion_pcie_master_slave_enable(void) -{ - orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER | - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY); -} - -static void orion_pcie_enable_interrupts(void) -{ - /* - * Enable interrupts lines - * INTA[24] INTB[25] INTC[26] INTD[27] - */ - orion_setbits(PCIE_MASK, 0xf<<24); -} - -static int orion_pcie_valid_config(u32 bus, u32 dev) +static int pcie_valid_config(int bus, int dev) { /* * Don't go out when trying to access -- - * 1. our own device + * 1. our own device / nonexisting device on local bus * 2. where there's no device connected (no link) - * 3. nonexisting devices on local bus */ - - if ((orion_pcie_local_bus_nr() == bus) && - (orion_pcie_local_dev_nr() == dev)) - return 0; - - if (orion_pcie_no_link()) + if (bus == 0 && dev != 1) return 0; - if (bus == orion_pcie_local_bus_nr()) - if (((orion_pcie_local_dev_nr() == 0) && (dev != 1)) || - ((orion_pcie_local_dev_nr() != 0) && (dev != 0))) + if (!orion_pcie_link_up(PCIE_BASE)) return 0; return 1; } -static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, - int size, u32 *val) + +/* + * PCIE config cycles are done by programming the PCIE_CONF_ADDR register + * and then reading the PCIE_CONF_DATA register. Need to make sure these + * transactions are atomic. + */ +static DEFINE_SPINLOCK(orion_pcie_lock); + +static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) { unsigned long flags; - unsigned int dev, rev, pcie_addr; + int ret; - if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { + if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { *val = 0xffffffff; return PCIBIOS_DEVICE_NOT_FOUND; } spin_lock_irqsave(&orion_pcie_lock, flags); + ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); + spin_unlock_irqrestore(&orion_pcie_lock, flags); - orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) | - PCIE_CONF_DEV(PCI_SLOT(devfn)) | - PCIE_CONF_FUNC(PCI_FUNC(devfn)) | - PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN); + return ret; +} - orion_pcie_id(&dev, &rev); - if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { - /* extended register space */ - pcie_addr = ORION_PCIE_WA_VIRT_BASE; - pcie_addr |= PCIE_CONF_BUS(bus->number) | - PCIE_CONF_DEV(PCI_SLOT(devfn)) | - PCIE_CONF_FUNC(PCI_FUNC(devfn)) | - PCIE_CONF_REG(where); - *val = orion_read(pcie_addr); - } else - *val = orion_read(PCIE_CONF_DATA); +static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, + int where, int size, u32 *val) +{ + int ret; - if (size == 1) - *val = (*val >> (8*(where & 0x3))) & 0xff; - else if (size == 2) - *val = (*val >> (8*(where & 0x3))) & 0xffff; + if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } - spin_unlock_irqrestore(&orion_pcie_lock, flags); + /* + * We only support access to the non-extended configuration + * space when using the WA access method (or we would have to + * sacrifice 256M of CPU virtual address space.) + */ + if (where >= 0x100) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } - return PCIBIOS_SUCCESSFUL; -} + ret = orion_pcie_rd_conf_wa((void __iomem *)ORION_PCIE_WA_VIRT_BASE, + bus, devfn, where, size, val); + return ret; +} -static int orion_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, - int size, u32 val) +static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, + int where, int size, u32 val) { unsigned long flags; int ret; - if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) + if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) return PCIBIOS_DEVICE_NOT_FOUND; spin_lock_irqsave(&orion_pcie_lock, flags); - - ret = PCIBIOS_SUCCESSFUL; - - orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) | - PCIE_CONF_DEV(PCI_SLOT(devfn)) | - PCIE_CONF_FUNC(PCI_FUNC(devfn)) | - PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN); - - if (size == 4) { - __raw_writel(val, PCIE_CONF_DATA); - } else if (size == 2) { - __raw_writew(val, PCIE_CONF_DATA + (where & 0x3)); - } else if (size == 1) { - __raw_writeb(val, PCIE_CONF_DATA + (where & 0x3)); - } else { - ret = PCIBIOS_BAD_REGISTER_NUMBER; - } - + ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); spin_unlock_irqrestore(&orion_pcie_lock, flags); return ret; } -struct pci_ops orion_pcie_ops = { - .read = orion_pcie_rd_conf, - .write = orion_pcie_wr_conf, +struct pci_ops pcie_ops = { + .read = pcie_rd_conf, + .write = pcie_wr_conf, }; -static int orion_pcie_setup(struct pci_sys_data *sys) +static int pcie_setup(struct pci_sys_data *sys) { struct resource *res; + int dev; /* - * Point PCIe unit MBUS decode windows to DRAM space. - */ - orion_setup_pcie_wins(&orion_mbus_dram_info); - - /* - * Master + Slave enable + * Generic PCIe unit setup. */ - orion_pcie_master_slave_enable(); + orion_pcie_setup(PCIE_BASE, &orion_mbus_dram_info); /* - * Enable interrupts lines A-D + * Check whether to apply Orion-1/Orion-NAS PCIe config + * read transaction workaround. */ - orion_pcie_enable_interrupts(); + dev = orion_pcie_dev_id(PCIE_BASE); + if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { + printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " + "read transaction workaround\n"); + pcie_ops.read = pcie_rd_conf_wa; + } /* - * Request resource + * Request resources. */ res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); if (!res) - panic("orion_pci_setup unable to alloc resources"); + panic("pcie_setup unable to alloc resources"); /* * IORESOURCE_IO @@ -417,19 +266,19 @@ static int orion_pcie_setup(struct pci_sys_data *sys) */ static DEFINE_SPINLOCK(orion_pci_lock); -u32 orion_pci_local_bus_nr(void) +int orion_pci_local_bus_nr(void) { u32 conf = orion_read(PCI_P2P_CONF); return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); } -static u32 orion_pci_local_dev_nr(void) +static int orion_pci_local_dev_nr(void) { u32 conf = orion_read(PCI_P2P_CONF); return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS); } -static int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, +static int orion_pci_hw_rd_conf(int bus, int dev, u32 func, u32 where, u32 size, u32 *val) { unsigned long flags; @@ -451,7 +300,7 @@ static int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, return PCIBIOS_SUCCESSFUL; } -static int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, +static int orion_pci_hw_wr_conf(int bus, int dev, u32 func, u32 where, u32 size, u32 val) { unsigned long flags; @@ -508,7 +357,7 @@ static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn, PCI_FUNC(devfn), where, size, val); } -struct pci_ops orion_pci_ops = { +struct pci_ops pci_ops = { .read = orion_pci_rd_conf, .write = orion_pci_wr_conf, }; @@ -540,7 +389,8 @@ static void orion_pci_set_bus_nr(int nr) static void orion_pci_master_slave_enable(void) { - u32 bus_nr, dev_nr, func, reg, val; + int bus_nr, dev_nr, func, reg; + u32 val; bus_nr = orion_pci_local_bus_nr(); dev_nr = orion_pci_local_dev_nr(); @@ -554,8 +404,8 @@ static void orion_pci_master_slave_enable(void) static void orion_setup_pci_wins(struct mbus_dram_target_info *dram) { u32 win_enable; - u32 bus; - u32 dev; + int bus; + int dev; int i; /* @@ -611,7 +461,7 @@ static void orion_setup_pci_wins(struct mbus_dram_target_info *dram) orion_setbits(PCI_ADDR_DECODE_CTRL, 1); } -static int orion_pci_setup(struct pci_sys_data *sys) +static int pci_setup(struct pci_sys_data *sys) { struct resource *res; @@ -635,7 +485,7 @@ static int orion_pci_setup(struct pci_sys_data *sys) */ res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); if (!res) - panic("orion_pci_setup unable to alloc resources"); + panic("pci_setup unable to alloc resources"); /* * IORESOURCE_IO @@ -674,16 +524,11 @@ int orion_pci_sys_setup(int nr, struct pci_sys_data *sys) int ret = 0; if (nr == 0) { - /* - * PCIE setup - */ - orion_pcie_set_bus_nr(0); - ret = orion_pcie_setup(sys); + orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); + ret = pcie_setup(sys); } else if (nr == 1) { - /* - * PCI setup - */ - ret = orion_pci_setup(sys); + orion_pci_set_bus_nr(sys->busnr); + ret = pci_setup(sys); } return ret; @@ -691,31 +536,15 @@ int orion_pci_sys_setup(int nr, struct pci_sys_data *sys) struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) { - struct pci_ops *ops; struct pci_bus *bus; - if (nr == 0) { - u32 pci_bus; - /* - * PCIE scan - */ - ops = &orion_pcie_ops; - bus = pci_scan_bus(sys->busnr, ops, sys); - /* - * Set local PCI bus number to follow PCIE bridges (if any) - */ - pci_bus = bus->number + bus->subordinate - bus->secondary + 1; - orion_pci_set_bus_nr(pci_bus); + bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); } else if (nr == 1) { - /* - * PCI scan - */ - ops = &orion_pci_ops; - bus = pci_scan_bus(sys->busnr, ops, sys); + bus = pci_scan_bus(sys->busnr, &pci_ops, sys); } else { - BUG(); bus = NULL; + BUG(); } return bus; diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile index ea4ce342a19..b33ecb60183 100644 --- a/arch/arm/plat-orion/Makefile +++ b/arch/arm/plat-orion/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := irq.o +obj-y := irq.o pcie.o obj-m := obj-n := obj- := diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c new file mode 100644 index 00000000000..f01966a330e --- /dev/null +++ b/arch/arm/plat-orion/pcie.c @@ -0,0 +1,245 @@ +/* + * arch/arm/plat-orion/pcie.c + * + * Marvell Orion SoC PCIe handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +/* + * PCIe unit register offsets. + */ +#define PCIE_DEV_ID_OFF 0x0000 +#define PCIE_CMD_OFF 0x0004 +#define PCIE_DEV_REV_OFF 0x0008 +#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) +#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) +#define PCIE_HEADER_LOG_4_OFF 0x0128 +#define PCIE_BAR_CTRL_OFF(n) (0x1804 + ((n - 1) * 4)) +#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) +#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) +#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) +#define PCIE_WIN5_CTRL_OFF 0x1880 +#define PCIE_WIN5_BASE_OFF 0x1884 +#define PCIE_WIN5_REMAP_OFF 0x188c +#define PCIE_CONF_ADDR_OFF 0x18f8 +#define PCIE_CONF_ADDR_EN 0x80000000 +#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) +#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) +#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) +#define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8) +#define PCIE_CONF_DATA_OFF 0x18fc +#define PCIE_MASK_OFF 0x1910 +#define PCIE_CTRL_OFF 0x1a00 +#define PCIE_STAT_OFF 0x1a04 +#define PCIE_STAT_DEV_OFFS 20 +#define PCIE_STAT_DEV_MASK 0x1f +#define PCIE_STAT_BUS_OFFS 8 +#define PCIE_STAT_BUS_MASK 0xff +#define PCIE_STAT_LINK_DOWN 1 + + +u32 __init orion_pcie_dev_id(void __iomem *base) +{ + return readl(base + PCIE_DEV_ID_OFF) >> 16; +} + +u32 __init orion_pcie_rev(void __iomem *base) +{ + return readl(base + PCIE_DEV_REV_OFF) & 0xff; +} + +int __init orion_pcie_link_up(void __iomem *base) +{ + return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); +} + +int __init orion_pcie_get_local_bus_nr(void __iomem *base) +{ + u32 stat = readl(base + PCIE_STAT_OFF); + + return (stat >> PCIE_STAT_BUS_OFFS) & PCIE_STAT_BUS_MASK; +} + +void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr) +{ + u32 stat; + + stat = readl(base + PCIE_STAT_OFF); + stat &= ~(PCIE_STAT_BUS_MASK << PCIE_STAT_BUS_OFFS); + stat |= nr << PCIE_STAT_BUS_OFFS; + writel(stat, base + PCIE_STAT_OFF); +} + +/* + * Setup PCIE BARs and Address Decode Wins: + * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks + * WIN[0-3] -> DRAM bank[0-3] + */ +static void __init orion_pcie_setup_wins(void __iomem *base, + struct mbus_dram_target_info *dram) +{ + u32 size; + int i; + + /* + * First, disable and clear BARs and windows. + */ + for (i = 1; i <= 2; i++) { + writel(0, base + PCIE_BAR_CTRL_OFF(i)); + writel(0, base + PCIE_BAR_LO_OFF(i)); + writel(0, base + PCIE_BAR_HI_OFF(i)); + } + + for (i = 0; i < 5; i++) { + writel(0, base + PCIE_WIN04_CTRL_OFF(i)); + writel(0, base + PCIE_WIN04_BASE_OFF(i)); + writel(0, base + PCIE_WIN04_REMAP_OFF(i)); + } + + writel(0, base + PCIE_WIN5_CTRL_OFF); + writel(0, base + PCIE_WIN5_BASE_OFF); + writel(0, base + PCIE_WIN5_REMAP_OFF); + + /* + * Setup windows for DDR banks. Count total DDR size on the fly. + */ + size = 0; + for (i = 0; i < dram->num_cs; i++) { + struct mbus_dram_window *cs = dram->cs + i; + + writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); + writel(0, base + PCIE_WIN04_REMAP_OFF(i)); + writel(((cs->size - 1) & 0xffff0000) | + (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1, + base + PCIE_WIN04_CTRL_OFF(i)); + + size += cs->size; + } + + /* + * Setup BAR[1] to all DRAM banks. + */ + writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1)); + writel(0, base + PCIE_BAR_HI_OFF(1)); + writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1)); +} + +void __init orion_pcie_setup(void __iomem *base, + struct mbus_dram_target_info *dram) +{ + u16 cmd; + u32 mask; + + /* + * Point PCIe unit MBUS decode windows to DRAM space. + */ + orion_pcie_setup_wins(base, dram); + + /* + * Master + slave enable. + */ + cmd = readw(base + PCIE_CMD_OFF); + cmd |= PCI_COMMAND_IO; + cmd |= PCI_COMMAND_MEMORY; + cmd |= PCI_COMMAND_MASTER; + writew(cmd, base + PCIE_CMD_OFF); + + /* + * Enable interrupt lines A-D. + */ + mask = readl(base + PCIE_MASK_OFF); + mask |= 0x0f000000; + writel(mask, base + PCIE_MASK_OFF); +} + +int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, + u32 devfn, int where, int size, u32 *val) +{ + writel(PCIE_CONF_BUS(bus->number) | + PCIE_CONF_DEV(PCI_SLOT(devfn)) | + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | + PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN, + base + PCIE_CONF_ADDR_OFF); + + *val = readl(base + PCIE_CONF_DATA_OFF); + + if (size == 1) + *val = (*val >> (8 * (where & 3))) & 0xff; + else if (size == 2) + *val = (*val >> (8 * (where & 3))) & 0xffff; + + return PCIBIOS_SUCCESSFUL; +} + +int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, + u32 devfn, int where, int size, u32 *val) +{ + writel(PCIE_CONF_BUS(bus->number) | + PCIE_CONF_DEV(PCI_SLOT(devfn)) | + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | + PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN, + base + PCIE_CONF_ADDR_OFF); + + *val = readl(base + PCIE_CONF_DATA_OFF); + + if (bus->number != orion_pcie_get_local_bus_nr(base) || + PCI_FUNC(devfn) != 0) + *val = readl(base + PCIE_HEADER_LOG_4_OFF); + + if (size == 1) + *val = (*val >> (8 * (where & 3))) & 0xff; + else if (size == 2) + *val = (*val >> (8 * (where & 3))) & 0xffff; + + return PCIBIOS_SUCCESSFUL; +} + +int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus, + u32 devfn, int where, int size, u32 *val) +{ + *val = readl(wa_base + (PCIE_CONF_BUS(bus->number) | + PCIE_CONF_DEV(PCI_SLOT(devfn)) | + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | + PCIE_CONF_REG(where))); + + if (size == 1) + *val = (*val >> (8 * (where & 3))) & 0xff; + else if (size == 2) + *val = (*val >> (8 * (where & 3))) & 0xffff; + + return PCIBIOS_SUCCESSFUL; +} + +int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus, + u32 devfn, int where, int size, u32 val) +{ + int ret = PCIBIOS_SUCCESSFUL; + + writel(PCIE_CONF_BUS(bus->number) | + PCIE_CONF_DEV(PCI_SLOT(devfn)) | + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | + PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN, + base + PCIE_CONF_ADDR_OFF); + + if (size == 4) { + writel(val, base + PCIE_CONF_DATA_OFF); + } else if (size == 2) { + writew(val, base + PCIE_CONF_DATA_OFF + (where & 3)); + } else if (size == 1) { + writeb(val, base + PCIE_CONF_DATA_OFF + (where & 3)); + } else { + ret = PCIBIOS_BAD_REGISTER_NUMBER; + } + + return ret; +} diff --git a/include/asm-arm/plat-orion/pcie.h b/include/asm-arm/plat-orion/pcie.h new file mode 100644 index 00000000000..6434ac685d2 --- /dev/null +++ b/include/asm-arm/plat-orion/pcie.h @@ -0,0 +1,31 @@ +/* + * include/asm-arm/plat-orion/pcie.h + * + * Marvell Orion SoC PCIe handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_PLAT_ORION_PCIE_H +#define __ASM_PLAT_ORION_PCIE_H + +u32 orion_pcie_dev_id(void __iomem *base); +u32 orion_pcie_rev(void __iomem *base); +int orion_pcie_link_up(void __iomem *base); +int orion_pcie_get_local_bus_nr(void __iomem *base); +void orion_pcie_set_local_bus_nr(void __iomem *base, int nr); +void orion_pcie_setup(void __iomem *base, + struct mbus_dram_target_info *dram); +int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, + u32 devfn, int where, int size, u32 *val); +int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, + u32 devfn, int where, int size, u32 *val); +int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus, + u32 devfn, int where, int size, u32 *val); +int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus, + u32 devfn, int where, int size, u32 val); + + +#endif -- GitLab From 2bac1de2031aa4cad88a437d4410ec289da4f7dc Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:40 -0400 Subject: [PATCH 013/212] plat-orion: share time handling code Split off Orion time handling code into plat-orion/. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/Makefile | 2 +- arch/arm/mach-orion/common.c | 16 +++ arch/arm/mach-orion/common.h | 6 +- arch/arm/mach-orion/time.c | 181 ------------------------- arch/arm/plat-orion/Makefile | 2 +- arch/arm/plat-orion/time.c | 203 +++++++++++++++++++++++++++++ include/asm-arm/arch-orion/orion.h | 7 +- include/asm-arm/arch-orion/timex.h | 3 +- include/asm-arm/plat-orion/time.h | 17 +++ 9 files changed, 245 insertions(+), 192 deletions(-) delete mode 100644 arch/arm/mach-orion/time.c create mode 100644 arch/arm/plat-orion/time.c create mode 100644 include/asm-arm/plat-orion/time.h diff --git a/arch/arm/mach-orion/Makefile b/arch/arm/mach-orion/Makefile index f91d937a73e..d894caa5060 100644 --- a/arch/arm/mach-orion/Makefile +++ b/arch/arm/mach-orion/Makefile @@ -1,4 +1,4 @@ -obj-y += common.o addr-map.o pci.o gpio.o irq.o time.o +obj-y += common.o addr-map.o pci.o gpio.o irq.o obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index a32fe8e108b..86d7f7ccfae 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -23,8 +23,11 @@ #include #include #include +#include #include +#include #include +#include #include "common.h" /***************************************************************************** @@ -295,6 +298,19 @@ void __init orion_sata_init(struct mv_sata_platform_data *sata_data) platform_device_register(&orion_sata); } +/***************************************************************************** + * Time handling + ****************************************************************************/ + +static void orion_timer_init(void) +{ + orion_time_init(IRQ_ORION_BRIDGE, ORION_TCLK); +} + +struct sys_timer orion_timer = { + .init = orion_timer_init, +}; + /***************************************************************************** * General ****************************************************************************/ diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h index 9a5afefac4d..3898e1b78ee 100644 --- a/arch/arm/mach-orion/common.h +++ b/arch/arm/mach-orion/common.h @@ -8,6 +8,7 @@ void __init orion_map_io(void); void __init orion_init_irq(void); void __init orion_init(void); +extern struct sys_timer orion_timer; /* * Enumerations and functions for Orion windows mapping. Used by Orion core @@ -56,11 +57,6 @@ struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); void __init orion_gpio_set_valid_pins(u32 pins); void gpio_display(void); /* debug */ -/* - * Orion system timer (clocksource + clockevnt, /mach-orion/time.c) - */ -extern struct sys_timer orion_timer; - /* * Pull in Orion Ethernet platform_data, used by machine-setup */ diff --git a/arch/arm/mach-orion/time.c b/arch/arm/mach-orion/time.c deleted file mode 100644 index bd4262da4f4..00000000000 --- a/arch/arm/mach-orion/time.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * arch/arm/mach-orion/time.c - * - * Core time functions for Marvell Orion System On Chip - * - * Maintainer: Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include "common.h" - -/* - * Timer0: clock_event_device, Tick. - * Timer1: clocksource, Free running. - * WatchDog: Not used. - * - * Timers are counting down. - */ -#define CLOCKEVENT 0 -#define CLOCKSOURCE 1 - -/* - * Timers bits - */ -#define BRIDGE_INT_TIMER(x) (1 << ((x) + 1)) -#define TIMER_EN(x) (1 << ((x) * 2)) -#define TIMER_RELOAD_EN(x) (1 << (((x) * 2) + 1)) -#define BRIDGE_INT_TIMER_WD (1 << 3) -#define TIMER_WD_EN (1 << 4) -#define TIMER_WD_RELOAD_EN (1 << 5) - -static cycle_t orion_clksrc_read(void) -{ - return (0xffffffff - orion_read(TIMER_VAL(CLOCKSOURCE))); -} - -static struct clocksource orion_clksrc = { - .name = "orion_clocksource", - .shift = 20, - .rating = 300, - .read = orion_clksrc_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static int -orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) -{ - unsigned long flags; - - if (delta == 0) - return -ETIME; - - local_irq_save(flags); - - /* - * Clear and enable timer interrupt bit - */ - orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT)); - orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT)); - - /* - * Setup new timer value - */ - orion_write(TIMER_VAL(CLOCKEVENT), delta); - - /* - * Disable auto reload and kickoff the timer - */ - orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT)); - orion_setbits(TIMER_CTRL, TIMER_EN(CLOCKEVENT)); - - local_irq_restore(flags); - - return 0; -} - -static void -orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) -{ - unsigned long flags; - - local_irq_save(flags); - - if (mode == CLOCK_EVT_MODE_PERIODIC) { - /* - * Setup latch cycles in timer and enable reload interrupt. - */ - orion_write(TIMER_VAL_RELOAD(CLOCKEVENT), LATCH); - orion_write(TIMER_VAL(CLOCKEVENT), LATCH); - orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT)); - orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) | - TIMER_EN(CLOCKEVENT)); - } else { - /* - * Disable timer and interrupt - */ - orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT)); - orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT)); - orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) | - TIMER_EN(CLOCKEVENT)); - } - - local_irq_restore(flags); -} - -static struct clock_event_device orion_clkevt = { - .name = "orion_tick", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, - .rating = 300, - .cpumask = CPU_MASK_CPU0, - .set_next_event = orion_clkevt_next_event, - .set_mode = orion_clkevt_mode, -}; - -static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) -{ - /* - * Clear cause bit and do event - */ - orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT)); - orion_clkevt.event_handler(&orion_clkevt); - return IRQ_HANDLED; -} - -static struct irqaction orion_timer_irq = { - .name = "orion_tick", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = orion_timer_interrupt -}; - -static void orion_timer_init(void) -{ - /* - * Setup clocksource free running timer (no interrupt on reload) - */ - orion_write(TIMER_VAL(CLOCKSOURCE), 0xffffffff); - orion_write(TIMER_VAL_RELOAD(CLOCKSOURCE), 0xffffffff); - orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKSOURCE)); - orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKSOURCE) | - TIMER_EN(CLOCKSOURCE)); - - /* - * Register clocksource - */ - orion_clksrc.mult = - clocksource_hz2mult(CLOCK_TICK_RATE, orion_clksrc.shift); - - clocksource_register(&orion_clksrc); - - /* - * Connect and enable tick handler - */ - setup_irq(IRQ_ORION_BRIDGE, &orion_timer_irq); - - /* - * Register clockevent - */ - orion_clkevt.mult = - div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, orion_clkevt.shift); - orion_clkevt.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &orion_clkevt); - orion_clkevt.min_delta_ns = - clockevent_delta2ns(1, &orion_clkevt); - - clockevents_register_device(&orion_clkevt); -} - -struct sys_timer orion_timer = { - .init = orion_timer_init, -}; diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile index b33ecb60183..198f3dde2be 100644 --- a/arch/arm/plat-orion/Makefile +++ b/arch/arm/plat-orion/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := irq.o pcie.o +obj-y := irq.o pcie.o time.o obj-m := obj-n := obj- := diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c new file mode 100644 index 00000000000..28b5285446e --- /dev/null +++ b/arch/arm/plat-orion/time.c @@ -0,0 +1,203 @@ +/* + * arch/arm/plat-orion/time.c + * + * Marvell Orion SoC timer handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Timer 0 is used as free-running clocksource, while timer 1 is + * used as clock_event_device. + */ + +#include +#include +#include +#include +#include +#include + +/* + * Number of timer ticks per jiffy. + */ +static u32 ticks_per_jiffy; + + +/* + * Timer block registers. + */ +#define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000) +#define TIMER0_EN 0x0001 +#define TIMER0_RELOAD_EN 0x0002 +#define TIMER1_EN 0x0004 +#define TIMER1_RELOAD_EN 0x0008 +#define TIMER0_RELOAD (TIMER_VIRT_BASE + 0x0010) +#define TIMER0_VAL (TIMER_VIRT_BASE + 0x0014) +#define TIMER1_RELOAD (TIMER_VIRT_BASE + 0x0018) +#define TIMER1_VAL (TIMER_VIRT_BASE + 0x001c) + + +/* + * Clocksource handling. + */ +static cycle_t orion_clksrc_read(void) +{ + return 0xffffffff - readl(TIMER0_VAL); +} + +static struct clocksource orion_clksrc = { + .name = "orion_clocksource", + .shift = 20, + .rating = 300, + .read = orion_clksrc_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + + + +/* + * Clockevent handling. + */ +static int +orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) +{ + unsigned long flags; + u32 u; + + if (delta == 0) + return -ETIME; + + local_irq_save(flags); + + /* + * Clear and enable clockevent timer interrupt. + */ + writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); + + u = readl(BRIDGE_MASK); + u |= BRIDGE_INT_TIMER1; + writel(u, BRIDGE_MASK); + + /* + * Setup new clockevent timer value. + */ + writel(delta, TIMER1_VAL); + + /* + * Enable the timer. + */ + u = readl(TIMER_CTRL); + u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN; + writel(u, TIMER_CTRL); + + local_irq_restore(flags); + + return 0; +} + +static void +orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) +{ + unsigned long flags; + u32 u; + + local_irq_save(flags); + if (mode == CLOCK_EVT_MODE_PERIODIC) { + /* + * Setup timer to fire at 1/HZ intervals. + */ + writel(ticks_per_jiffy - 1, TIMER1_RELOAD); + writel(ticks_per_jiffy - 1, TIMER1_VAL); + + /* + * Enable timer interrupt. + */ + u = readl(BRIDGE_MASK); + writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK); + + /* + * Enable timer. + */ + u = readl(TIMER_CTRL); + writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL); + } else { + /* + * Disable timer. + */ + u = readl(TIMER_CTRL); + writel(u & ~TIMER1_EN, TIMER_CTRL); + + /* + * Disable timer interrupt. + */ + u = readl(BRIDGE_MASK); + writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK); + + /* + * ACK pending timer interrupt. + */ + writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); + + } + local_irq_restore(flags); +} + +static struct clock_event_device orion_clkevt = { + .name = "orion_tick", + .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, + .shift = 32, + .rating = 300, + .cpumask = CPU_MASK_CPU0, + .set_next_event = orion_clkevt_next_event, + .set_mode = orion_clkevt_mode, +}; + +static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) +{ + /* + * ACK timer interrupt and call event handler. + */ + writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); + orion_clkevt.event_handler(&orion_clkevt); + + return IRQ_HANDLED; +} + +static struct irqaction orion_timer_irq = { + .name = "orion_tick", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = orion_timer_interrupt +}; + +void __init orion_time_init(unsigned int irq, unsigned int tclk) +{ + u32 u; + + ticks_per_jiffy = (tclk + HZ/2) / HZ; + + + /* + * Setup free-running clocksource timer (interrupts + * disabled.) + */ + writel(0xffffffff, TIMER0_VAL); + writel(0xffffffff, TIMER0_RELOAD); + u = readl(BRIDGE_MASK); + writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK); + u = readl(TIMER_CTRL); + writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL); + orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift); + clocksource_register(&orion_clksrc); + + + /* + * Setup clockevent timer (interrupt-driven.) + */ + setup_irq(irq, &orion_timer_irq); + orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift); + orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt); + orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt); + clockevents_register_device(&orion_clkevt); +} diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h index 673a418a741..884f3e2717d 100644 --- a/include/asm-arm/arch-orion/orion.h +++ b/include/asm-arm/arch-orion/orion.h @@ -137,11 +137,12 @@ #define POWER_MNG_CTRL_REG ORION_BRIDGE_REG(0x11C) #define BRIDGE_CAUSE ORION_BRIDGE_REG(0x110) #define BRIDGE_MASK ORION_BRIDGE_REG(0x114) +#define BRIDGE_INT_TIMER0 0x0002 +#define BRIDGE_INT_TIMER1 0x0004 #define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200) #define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204) -#define TIMER_CTRL ORION_BRIDGE_REG(0x300) -#define TIMER_VAL(x) ORION_BRIDGE_REG(0x314 + ((x) * 8)) -#define TIMER_VAL_RELOAD(x) ORION_BRIDGE_REG(0x310 + ((x) * 8)) + +#define TIMER_VIRT_BASE (ORION_BRIDGE_VIRT_BASE | 0x300) #ifndef __ASSEMBLY__ diff --git a/include/asm-arm/arch-orion/timex.h b/include/asm-arm/arch-orion/timex.h index 26c2c91eecf..cc0fc7075eb 100644 --- a/include/asm-arm/arch-orion/timex.h +++ b/include/asm-arm/arch-orion/timex.h @@ -8,5 +8,6 @@ * warranty of any kind, whether express or implied. */ +#define CLOCK_TICK_RATE (100 * HZ) + #define ORION_TCLK 166666667 -#define CLOCK_TICK_RATE ORION_TCLK diff --git a/include/asm-arm/plat-orion/time.h b/include/asm-arm/plat-orion/time.h new file mode 100644 index 00000000000..0e85cc8f44d --- /dev/null +++ b/include/asm-arm/plat-orion/time.h @@ -0,0 +1,17 @@ +/* + * include/asm-arm/plat-orion/time.h + * + * Marvell Orion SoC time handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_PLAT_ORION_TIME_H +#define __ASM_PLAT_ORION_TIME_H + +void orion_time_init(unsigned int irq, unsigned int tclk); + + +#endif -- GitLab From 705a752162768fed3e2c26fba5bffdd3a3bd04f2 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:40 -0400 Subject: [PATCH 014/212] plat-orion: make ehci-orion available for all Orion families Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/common.c | 1 + drivers/usb/host/ehci-hcd.c | 2 +- drivers/usb/host/ehci-orion.c | 3 +-- include/asm-arm/arch-orion/platform.h | 8 -------- include/asm-arm/plat-orion/ehci-orion.h | 19 +++++++++++++++++++ 5 files changed, 22 insertions(+), 11 deletions(-) create mode 100644 include/asm-arm/plat-orion/ehci-orion.h diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index 86d7f7ccfae..1e124b7b0bd 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include "common.h" diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 46ee7f4c091..85074cb36f3 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1033,7 +1033,7 @@ MODULE_LICENSE ("GPL"); #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver #endif -#ifdef CONFIG_ARCH_ORION +#ifdef CONFIG_PLAT_ORION #include "ehci-orion.c" #define PLATFORM_DRIVER ehci_orion_driver #endif diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c index 0f0eb89c8cf..d187d031374 100644 --- a/drivers/usb/host/ehci-orion.c +++ b/drivers/usb/host/ehci-orion.c @@ -12,8 +12,7 @@ #include #include #include -#include -#include +#include #define rdl(off) __raw_readl(hcd->regs + (off)) #define wrl(off, val) __raw_writel((val), hcd->regs + (off)) diff --git a/include/asm-arm/arch-orion/platform.h b/include/asm-arm/arch-orion/platform.h index 0e33fe536ef..4e09c6c1af4 100644 --- a/include/asm-arm/arch-orion/platform.h +++ b/include/asm-arm/arch-orion/platform.h @@ -11,14 +11,6 @@ #ifndef __ASM_ARCH_PLATFORM_H__ #define __ASM_ARCH_PLATFORM_H__ -/* - * Orion EHCI platform driver data. - */ -struct orion_ehci_data { - struct mbus_dram_target_info *dram; -}; - - /* * Device bus NAND private data */ diff --git a/include/asm-arm/plat-orion/ehci-orion.h b/include/asm-arm/plat-orion/ehci-orion.h new file mode 100644 index 00000000000..785705651e2 --- /dev/null +++ b/include/asm-arm/plat-orion/ehci-orion.h @@ -0,0 +1,19 @@ +/* + * include/asm-arm/plat-orion/ehci-orion.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_PLAT_ORION_EHCI_ORION_H +#define __ASM_PLAT_ORION_EHCI_ORION_H + +#include + +struct orion_ehci_data { + struct mbus_dram_target_info *dram; +}; + + +#endif -- GitLab From 83aac8a338520573104127b5180f46c11e9f02e7 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:40 -0400 Subject: [PATCH 015/212] plat-orion: make mv643xx_eth available for all Orion families Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- drivers/net/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index fe7b5ec0970..124d29f5fa0 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -2415,7 +2415,7 @@ config UGETH_TX_ON_DEMAND config MV643XX_ETH tristate "Marvell Discovery (643XX) and Orion ethernet support" - depends on MV64360 || MV64X60 || (PPC_MULTIPLATFORM && PPC32) || ARCH_ORION + depends on MV64360 || MV64X60 || (PPC_MULTIPLATFORM && PPC32) || PLAT_ORION select MII help This driver supports the gigabit ethernet MACs in the -- GitLab From 8791ed3295950b06a0edd8aea1d0717f66f3e5cf Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:40 -0400 Subject: [PATCH 016/212] plat-orion: make i2c-mv64xxx available for all Orion families Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- drivers/i2c/busses/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 5fa9c3c67e0..b04c99580d0 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -645,7 +645,7 @@ config I2C_PCA_ISA config I2C_MV64XXX tristate "Marvell mv64xxx I2C Controller" - depends on (MV64X60 || ARCH_ORION) && EXPERIMENTAL + depends on (MV64X60 || PLAT_ORION) && EXPERIMENTAL help If you say yes to this option, support will be included for the built-in I2C interface on the Marvell 64xxx line of host bridges. -- GitLab From 5d4294c524fc53746b5ec138d2e90f9d34d754b0 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:40 -0400 Subject: [PATCH 017/212] plat-orion: make orion_nand available for all Orion families Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/common.c | 2 +- arch/arm/mach-orion/db88f5281-setup.c | 2 +- arch/arm/mach-orion/dns323-setup.c | 1 - arch/arm/mach-orion/kurobox_pro-setup.c | 2 +- arch/arm/mach-orion/rd88f5182-setup.c | 1 - arch/arm/mach-orion/ts209-setup.c | 1 - drivers/mtd/nand/Kconfig | 2 +- drivers/mtd/nand/orion_nand.c | 2 +- .../{arch-orion/platform.h => plat-orion/orion_nand.h} | 10 ++++------ 9 files changed, 9 insertions(+), 14 deletions(-) rename include/asm-arm/{arch-orion/platform.h => plat-orion/orion_nand.h} (64%) diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index 1e124b7b0bd..1b5ed72899e 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -26,8 +26,8 @@ #include #include #include -#include #include +#include #include #include "common.h" diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion/db88f5281-setup.c index 5ef44e1a2d3..5cf65fedfae 100644 --- a/arch/arm/mach-orion/db88f5281-setup.c +++ b/arch/arm/mach-orion/db88f5281-setup.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include "common.h" /***************************************************************************** diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion/dns323-setup.c index 076e155ad51..38593784d76 100644 --- a/arch/arm/mach-orion/dns323-setup.c +++ b/arch/arm/mach-orion/dns323-setup.c @@ -26,7 +26,6 @@ #include #include #include -#include #include "common.h" #define DNS323_GPIO_LED_RIGHT_AMBER 1 diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion/kurobox_pro-setup.c index 785a07bdf1e..feae4839830 100644 --- a/arch/arm/mach-orion/kurobox_pro-setup.c +++ b/arch/arm/mach-orion/kurobox_pro-setup.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include "common.h" /***************************************************************************** diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion/rd88f5182-setup.c index e851b8ca5ac..e3cc757a4ca 100644 --- a/arch/arm/mach-orion/rd88f5182-setup.c +++ b/arch/arm/mach-orion/rd88f5182-setup.c @@ -25,7 +25,6 @@ #include #include #include -#include #include "common.h" /***************************************************************************** diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion/ts209-setup.c index 45764dad16d..86583e4856a 100644 --- a/arch/arm/mach-orion/ts209-setup.c +++ b/arch/arm/mach-orion/ts209-setup.c @@ -27,7 +27,6 @@ #include #include #include -#include #include "common.h" #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000 diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 4a3c6759492..959fb86cda0 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -314,7 +314,7 @@ config MTD_ALAUDA config MTD_NAND_ORION tristate "NAND Flash support for Marvell Orion SoC" - depends on ARCH_ORION && MTD_NAND + depends on PLAT_ORION && MTD_NAND help This enables the NAND flash controller on Orion machines. diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c index 9162cca0182..ec5ad28b237 100644 --- a/drivers/mtd/nand/orion_nand.c +++ b/drivers/mtd/nand/orion_nand.c @@ -18,8 +18,8 @@ #include #include #include -#include #include +#include #ifdef CONFIG_MTD_CMDLINE_PARTS static const char *part_probes[] = { "cmdlinepart", NULL }; diff --git a/include/asm-arm/arch-orion/platform.h b/include/asm-arm/plat-orion/orion_nand.h similarity index 64% rename from include/asm-arm/arch-orion/platform.h rename to include/asm-arm/plat-orion/orion_nand.h index 4e09c6c1af4..ffd3852a0dd 100644 --- a/include/asm-arm/arch-orion/platform.h +++ b/include/asm-arm/plat-orion/orion_nand.h @@ -1,15 +1,13 @@ /* - * asm-arm/arch-orion/platform.h - * - * Tzachi Perelstein + * include/asm-arm/plat-orion/orion_nand.h * * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#ifndef __ASM_ARCH_PLATFORM_H__ -#define __ASM_ARCH_PLATFORM_H__ +#ifndef __ASM_PLAT_ORION_ORION_NAND_H +#define __ASM_PLAT_ORION_ORION_NAND_H /* * Device bus NAND private data -- GitLab From 98f79d1ea0459b907f95846bad5e967a06b7a0d5 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:40 -0400 Subject: [PATCH 018/212] Orion: revamp cpu mbus window handling Instead of forcing all device bus window setup through one function with some enum as the first argument, create separate window setup functions for each of the four possible targets, and do the demux internally. This allows getting rid of the window identifier enum and the big switch statement in orion_setup_cpu_win(). Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/addr-map.c | 144 ++++++++---------------- arch/arm/mach-orion/common.c | 2 +- arch/arm/mach-orion/common.h | 23 +--- arch/arm/mach-orion/db88f5281-setup.c | 13 +-- arch/arm/mach-orion/dns323-setup.c | 7 +- arch/arm/mach-orion/kurobox_pro-setup.c | 12 +- arch/arm/mach-orion/rd88f5182-setup.c | 11 +- arch/arm/mach-orion/ts209-setup.c | 8 +- 8 files changed, 76 insertions(+), 144 deletions(-) diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c index 3de5de9ac65..ca641db6214 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion/addr-map.c @@ -25,10 +25,10 @@ * CPU address decoding -- * Linux assumes that it is the boot loader that already setup the access to * DDR and internal registers. - * Setup access to PCI and PCI-E IO/MEM space is issued by core.c. + * Setup access to PCI and PCI-E IO/MEM space is issued by this file. * Setup access to various devices located on the device bus interface (e.g. * flashes, RTC, etc) should be issued by machine-setup.c according to - * specific board population (by using orion_setup_cpu_win()). + * specific board population (by using orion_setup_*_win()). * * Non-CPU Masters address decoding -- * Unlike the CPU, we setup the access from Orion's master interfaces to DDR @@ -53,6 +53,7 @@ ((n) == 3) ? 0x7 : 0xf) #define ATTR_PCIE_MEM 0x59 #define ATTR_PCIE_IO 0x51 +#define ATTR_PCIE_WA 0x79 #define ATTR_PCI_MEM 0x59 #define ATTR_PCI_IO 0x51 #define ATTR_DEV_CS0 0x1e @@ -78,19 +79,6 @@ #define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4)) #define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4)) #define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4)) -#define CPU_MAX_WIN 8 - -/* - * Use this CPU address decode windows allocation - */ -#define CPU_WIN_PCIE_IO 0 -#define CPU_WIN_PCI_IO 1 -#define CPU_WIN_PCIE_MEM 2 -#define CPU_WIN_PCI_MEM 3 -#define CPU_WIN_DEV_BOOT 4 -#define CPU_WIN_DEV_CS0 5 -#define CPU_WIN_DEV_CS1 6 -#define CPU_WIN_DEV_CS2 7 /* * Gigabit Ethernet Address Decode Windows registers @@ -106,7 +94,7 @@ struct mbus_dram_target_info orion_mbus_dram_info; -static int __init orion_cpu_win_can_remap(u32 win) +static int __init orion_cpu_win_can_remap(int win) { u32 dev, rev; @@ -119,88 +107,31 @@ static int __init orion_cpu_win_can_remap(u32 win) return 0; } -void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap) +static void __init setup_cpu_win(int win, u32 base, u32 size, + u8 target, u8 attr, int remap) { - u32 win, attr, ctrl; - - switch (target) { - case ORION_PCIE_IO: - target = TARGET_PCIE; - attr = ATTR_PCIE_IO; - win = CPU_WIN_PCIE_IO; - break; - case ORION_PCI_IO: - target = TARGET_PCI; - attr = ATTR_PCI_IO; - win = CPU_WIN_PCI_IO; - break; - case ORION_PCIE_MEM: - target = TARGET_PCIE; - attr = ATTR_PCIE_MEM; - win = CPU_WIN_PCIE_MEM; - break; - case ORION_PCI_MEM: - target = TARGET_PCI; - attr = ATTR_PCI_MEM; - win = CPU_WIN_PCI_MEM; - break; - case ORION_DEV_BOOT: - target = TARGET_DEV_BUS; - attr = ATTR_DEV_BOOT; - win = CPU_WIN_DEV_BOOT; - break; - case ORION_DEV0: - target = TARGET_DEV_BUS; - attr = ATTR_DEV_CS0; - win = CPU_WIN_DEV_CS0; - break; - case ORION_DEV1: - target = TARGET_DEV_BUS; - attr = ATTR_DEV_CS1; - win = CPU_WIN_DEV_CS1; - break; - case ORION_DEV2: - target = TARGET_DEV_BUS; - attr = ATTR_DEV_CS2; - win = CPU_WIN_DEV_CS2; - break; - case ORION_DDR: - case ORION_REGS: - /* - * Must be mapped by bootloader. - */ - default: - target = attr = win = -1; - BUG(); - } - - base &= 0xffff0000; - ctrl = (((size - 1) & 0xffff0000) | (attr << 8) | - (target << 4) | WIN_EN); - - orion_write(CPU_WIN_BASE(win), base); - orion_write(CPU_WIN_CTRL(win), ctrl); + orion_write(CPU_WIN_BASE(win), base & 0xffff0000); + orion_write(CPU_WIN_CTRL(win), + ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1); if (orion_cpu_win_can_remap(win)) { - if (remap >= 0) { - orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); - orion_write(CPU_WIN_REMAP_HI(win), 0); - } else { - orion_write(CPU_WIN_REMAP_LO(win), base); - orion_write(CPU_WIN_REMAP_HI(win), 0); - } + if (remap < 0) + remap = base; + + orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); + orion_write(CPU_WIN_REMAP_HI(win), 0); } } -void __init orion_setup_cpu_wins(void) +void __init orion_setup_cpu_mbus_bridge(void) { int i; int cs; /* - * First, disable and clear windows + * First, disable and clear windows. */ - for (i = 0; i < CPU_MAX_WIN; i++) { + for (i = 0; i < 8; i++) { orion_write(CPU_WIN_BASE(i), 0); orion_write(CPU_WIN_CTRL(i), 0); if (orion_cpu_win_can_remap(i)) { @@ -212,14 +143,14 @@ void __init orion_setup_cpu_wins(void) /* * Setup windows for PCI+PCIe IO+MEM space. */ - orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE, - ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE); - orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE, - ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE); - orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE, - ORION_PCIE_MEM_SIZE, -1); - orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE, - ORION_PCI_MEM_SIZE, -1); + setup_cpu_win(0, ORION_PCIE_IO_PHYS_BASE, ORION_PCIE_IO_SIZE, + TARGET_PCIE, ATTR_PCIE_IO, ORION_PCIE_IO_BUS_BASE); + setup_cpu_win(1, ORION_PCI_IO_PHYS_BASE, ORION_PCI_IO_SIZE, + TARGET_PCI, ATTR_PCI_IO, ORION_PCI_IO_BUS_BASE); + setup_cpu_win(2, ORION_PCIE_MEM_PHYS_BASE, ORION_PCIE_MEM_SIZE, + TARGET_PCIE, ATTR_PCIE_MEM, -1); + setup_cpu_win(3, ORION_PCI_MEM_PHYS_BASE, ORION_PCI_MEM_SIZE, + TARGET_PCI, ATTR_PCI_MEM, -1); /* * Setup MBUS dram target info. @@ -246,6 +177,31 @@ void __init orion_setup_cpu_wins(void) orion_mbus_dram_info.num_cs = cs; } +void __init orion_setup_dev_boot_win(u32 base, u32 size) +{ + setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); +} + +void __init orion_setup_dev0_win(u32 base, u32 size) +{ + setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1); +} + +void __init orion_setup_dev1_win(u32 base, u32 size) +{ + setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1); +} + +void __init orion_setup_dev2_win(u32 base, u32 size) +{ + setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1); +} + +void __init orion_setup_pcie_wa_win(u32 base, u32 size) +{ + setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); +} + void __init orion_setup_eth_wins(void) { int i; diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index 1b5ed72899e..e271994d27f 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -359,7 +359,7 @@ void __init orion_init(void) /* * Setup Orion address map */ - orion_setup_cpu_wins(); + orion_setup_cpu_mbus_bridge(); orion_setup_eth_wins(); /* diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h index 3898e1b78ee..74f23e61c40 100644 --- a/arch/arm/mach-orion/common.h +++ b/arch/arm/mach-orion/common.h @@ -15,24 +15,13 @@ extern struct sys_timer orion_timer; * functions to map its interfaces and by the machine-setup to map its on- * board devices. Details in /mach-orion/addr-map.c */ - -enum orion_target { - ORION_DEV_BOOT = 0, - ORION_DEV0, - ORION_DEV1, - ORION_DEV2, - ORION_PCIE_MEM, - ORION_PCIE_IO, - ORION_PCI_MEM, - ORION_PCI_IO, - ORION_DDR, - ORION_REGS, - ORION_MAX_TARGETS -}; - extern struct mbus_dram_target_info orion_mbus_dram_info; -void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap); -void orion_setup_cpu_wins(void); +void orion_setup_cpu_mbus_bridge(void); +void orion_setup_dev_boot_win(u32 base, u32 size); +void orion_setup_dev0_win(u32 base, u32 size); +void orion_setup_dev1_win(u32 base, u32 size); +void orion_setup_dev2_win(u32 base, u32 size); +void orion_setup_pcie_wa_win(u32 base, u32 size); void orion_setup_eth_wins(void); /* diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion/db88f5281-setup.c index 5cf65fedfae..aad62efa1da 100644 --- a/arch/arm/mach-orion/db88f5281-setup.c +++ b/arch/arm/mach-orion/db88f5281-setup.c @@ -317,14 +317,11 @@ static void __init db88f5281_init(void) /* * Setup the CPU address decode windows for our on-board devices */ - orion_setup_cpu_win(ORION_DEV_BOOT, DB88F5281_NOR_BOOT_BASE, - DB88F5281_NOR_BOOT_SIZE, -1); - orion_setup_cpu_win(ORION_DEV0, DB88F5281_7SEG_BASE, - DB88F5281_7SEG_SIZE, -1); - orion_setup_cpu_win(ORION_DEV1, DB88F5281_NOR_BASE, - DB88F5281_NOR_SIZE, -1); - orion_setup_cpu_win(ORION_DEV2, DB88F5281_NAND_BASE, - DB88F5281_NAND_SIZE, -1); + orion_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, + DB88F5281_NOR_BOOT_SIZE); + orion_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); + orion_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); + orion_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); /* * Setup Multiplexing Pins: diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion/dns323-setup.c index 38593784d76..88991f76479 100644 --- a/arch/arm/mach-orion/dns323-setup.c +++ b/arch/arm/mach-orion/dns323-setup.c @@ -251,16 +251,13 @@ static void __init dns323_init(void) /* setup flash mapping * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 */ - orion_setup_cpu_win(ORION_DEV_BOOT, DNS323_NOR_BOOT_BASE, - DNS323_NOR_BOOT_SIZE, -1); + orion_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE * * Open a special address decode windows for the PCIE WA. */ - orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); - orion_write(ORION_REGS_VIRT_BASE | 0x20070, - (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); + orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ orion_write(MPP_0_7_CTRL, 0); diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion/kurobox_pro-setup.c index feae4839830..bf7034df8a6 100644 --- a/arch/arm/mach-orion/kurobox_pro-setup.c +++ b/arch/arm/mach-orion/kurobox_pro-setup.c @@ -193,16 +193,14 @@ static void __init kurobox_pro_init(void) /* * Setup the CPU address decode windows for our devices */ - orion_setup_cpu_win(ORION_DEV_BOOT, KUROBOX_PRO_NOR_BOOT_BASE, - KUROBOX_PRO_NOR_BOOT_SIZE, -1); - orion_setup_cpu_win(ORION_DEV0, KUROBOX_PRO_NAND_BASE, - KUROBOX_PRO_NAND_SIZE, -1); + orion_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, + KUROBOX_PRO_NOR_BOOT_SIZE); + orion_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE); + /* * Open a special address decode windows for the PCIE WA. */ - orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); - orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | - (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); + orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); /* * Setup Multiplexing Pins -- diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion/rd88f5182-setup.c index e3cc757a4ca..662c097ca33 100644 --- a/arch/arm/mach-orion/rd88f5182-setup.c +++ b/arch/arm/mach-orion/rd88f5182-setup.c @@ -254,17 +254,14 @@ static void __init rd88f5182_init(void) /* * Setup the CPU address decode windows for our devices */ - orion_setup_cpu_win(ORION_DEV_BOOT, RD88F5182_NOR_BOOT_BASE, - RD88F5182_NOR_BOOT_SIZE, -1); - orion_setup_cpu_win(ORION_DEV1, RD88F5182_NOR_BASE, - RD88F5182_NOR_SIZE, -1); + orion_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, + RD88F5182_NOR_BOOT_SIZE); + orion_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); /* * Open a special address decode windows for the PCIE WA. */ - orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); - orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | - (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); + orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); /* * Setup Multiplexing Pins -- diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion/ts209-setup.c index 86583e4856a..8eca070006f 100644 --- a/arch/arm/mach-orion/ts209-setup.c +++ b/arch/arm/mach-orion/ts209-setup.c @@ -288,15 +288,13 @@ static void __init qnap_ts209_init(void) /* * Setup flash mapping */ - orion_setup_cpu_win(ORION_DEV_BOOT, QNAP_TS209_NOR_BOOT_BASE, - QNAP_TS209_NOR_BOOT_SIZE, -1); + orion_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, + QNAP_TS209_NOR_BOOT_SIZE); /* * Open a special address decode windows for the PCIE WA. */ - orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); - orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | - (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); + orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); /* * Setup Multiplexing Pins -- -- GitLab From da14d88e90d476b315e5e9c3e3ffa940cb670c6d Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:40 -0400 Subject: [PATCH 019/212] Orion: describe physical address map Include a table describing our physical address map in orion.h. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- include/asm-arm/arch-orion/orion.h | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h index 884f3e2717d..95f67081bb9 100644 --- a/include/asm-arm/arch-orion/orion.h +++ b/include/asm-arm/arch-orion/orion.h @@ -15,13 +15,25 @@ #define __ASM_ARCH_ORION_H__ /***************************************************************************** - * Orion Address Map + * Orion Address Maps + * + * phys + * e0000000 PCIe MEM space + * e8000000 PCI MEM space + * f0000000 PCIe WA space (Orion-1/Orion-NAS only) + * f1000000 on-chip peripheral registers + * f2000000 PCIe I/O space + * f2100000 PCI I/O space + * f4000000 device bus mappings (boot) + * fa000000 device bus mappings (cs0) + * fa800000 device bus mappings (cs2) + * fc000000 device bus mappings (cs0/cs1) * * virt phys size * fdd00000 f1000000 1M on-chip peripheral registers * fde00000 f2000000 1M PCIe I/O space * fdf00000 f2100000 1M PCI I/O space - * fe000000 f0000000 16M PCIe WA space (Orion-NAS only) + * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) ****************************************************************************/ #define ORION_REGS_PHYS_BASE 0xf1000000 #define ORION_REGS_VIRT_BASE 0xfdd00000 @@ -37,7 +49,7 @@ #define ORION_PCI_IO_BUS_BASE 0x00100000 #define ORION_PCI_IO_SIZE SZ_1M -/* Relevant only for Orion-NAS */ +/* Relevant only for Orion-1/Orion-NAS */ #define ORION_PCIE_WA_PHYS_BASE 0xf0000000 #define ORION_PCIE_WA_VIRT_BASE 0xfe000000 #define ORION_PCIE_WA_SIZE SZ_16M -- GitLab From b590bc5cd0ced1019f02ca7c9b8594482304987f Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:41 -0400 Subject: [PATCH 020/212] Orion: move I/O macros out of orion.h Move the Orion register accessor macros out of orion.h, to prevent them from ending up in the decompressor image (Orion uncompress.h includes orion.h.) Move them into io.h, which seems a better place for this kind of stuff. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/addr-map.c | 1 + arch/arm/mach-orion/gpio.c | 1 + arch/arm/mach-orion/irq.c | 1 + include/asm-arm/arch-orion/io.h | 15 +++++++++++++++ include/asm-arm/arch-orion/orion.h | 20 +------------------- 5 files changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c index ca641db6214..ecca987b57e 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion/addr-map.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "common.h" /* diff --git a/arch/arm/mach-orion/gpio.c b/arch/arm/mach-orion/gpio.c index f713818c66a..5a7d9cc9b80 100644 --- a/arch/arm/mach-orion/gpio.c +++ b/arch/arm/mach-orion/gpio.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include "common.h" diff --git a/arch/arm/mach-orion/irq.c b/arch/arm/mach-orion/irq.c index 855793afcca..dc8cb15a817 100644 --- a/arch/arm/mach-orion/irq.c +++ b/arch/arm/mach-orion/irq.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include "common.h" diff --git a/include/asm-arm/arch-orion/io.h b/include/asm-arm/arch-orion/io.h index e0b8c39b916..42abd297ae5 100644 --- a/include/asm-arm/arch-orion/io.h +++ b/include/asm-arm/arch-orion/io.h @@ -24,4 +24,19 @@ static inline void __iomem *__io(unsigned long addr) #define __io(a) __io(a) #define __mem_pci(a) (a) + +/***************************************************************************** + * Helpers to access Orion registers + ****************************************************************************/ +#define orion_read(r) __raw_readl(r) +#define orion_write(r, val) __raw_writel(val, r) + +/* + * These are not preempt-safe. Locks, if needed, must be taken + * care of by the caller. + */ +#define orion_setbits(r, mask) orion_write((r), orion_read(r) | (mask)) +#define orion_clrbits(r, mask) orion_write((r), orion_read(r) & ~(mask)) + + #endif diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h index 95f67081bb9..d0b32c379ae 100644 --- a/include/asm-arm/arch-orion/orion.h +++ b/include/asm-arm/arch-orion/orion.h @@ -156,23 +156,5 @@ #define TIMER_VIRT_BASE (ORION_BRIDGE_VIRT_BASE | 0x300) -#ifndef __ASSEMBLY__ -/******************************************************************************* - * Helpers to access Orion registers - ******************************************************************************/ -#include -#include - -#define orion_read(r) __raw_readl(r) -#define orion_write(r, val) __raw_writel(val, r) - -/* - * These are not preempt safe. Locks, if needed, must be taken care by caller. - */ -#define orion_setbits(r, mask) orion_write((r), orion_read(r) | (mask)) -#define orion_clrbits(r, mask) orion_write((r), orion_read(r) & ~(mask)) - -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_ARCH_ORION_H__ */ +#endif -- GitLab From 1419468ab548f990b172740d77b5c1032a790114 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:41 -0400 Subject: [PATCH 021/212] Orion: only map peripheral register space once Save some TLB entries by making ioremap() return pointers into the boot-time Orion peripheral iotable mapping whenever someone tries to ioremap any part of the Orion peripheral register space. Signed-off-by: Lennert Buytenhek Reviewed-by: Nicolas Pitre Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- include/asm-arm/arch-orion/io.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/include/asm-arm/arch-orion/io.h b/include/asm-arm/arch-orion/io.h index 42abd297ae5..486dc04d764 100644 --- a/include/asm-arm/arch-orion/io.h +++ b/include/asm-arm/arch-orion/io.h @@ -16,11 +16,37 @@ #define IO_SPACE_LIMIT 0xffffffff #define IO_SPACE_REMAP ORION_PCI_SYS_IO_BASE +static inline void __iomem * +__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) +{ + void __iomem *retval; + + if (mtype == MT_DEVICE && size && paddr >= ORION_REGS_PHYS_BASE && + paddr + size <= ORION_REGS_PHYS_BASE + ORION_REGS_SIZE) { + retval = (void __iomem *)ORION_REGS_VIRT_BASE + + (paddr - ORION_REGS_PHYS_BASE); + } else { + retval = __arm_ioremap(paddr, size, mtype); + } + + return retval; +} + +static inline void +__arch_iounmap(void __iomem *addr) +{ + if (addr < (void __iomem *)ORION_REGS_VIRT_BASE || + addr >= (void __iomem *)(ORION_REGS_VIRT_BASE + ORION_REGS_SIZE)) + __iounmap(addr); +} + static inline void __iomem *__io(unsigned long addr) { return (void __iomem *)addr; } +#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m) +#define __arch_iounmap(a) __arch_iounmap(a) #define __io(a) __io(a) #define __mem_pci(a) (a) -- GitLab From a99842704a031ac23d4f7344e412a44bb3beb3b3 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:41 -0400 Subject: [PATCH 022/212] Orion: add __init attribute to all boot time-only functions Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/common.c | 2 +- arch/arm/mach-orion/pci.c | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index e271994d27f..aae157d360e 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -319,7 +319,7 @@ struct sys_timer orion_timer = { /* * Identify device ID and rev from PCIE configuration header space '0'. */ -static void orion_id(u32 *dev, u32 *rev, char **dev_name) +static void __init orion_id(u32 *dev, u32 *rev, char **dev_name) { orion_pcie_id(dev, rev); diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c index 5240a245c7e..18cdf3b505a 100644 --- a/arch/arm/mach-orion/pci.c +++ b/arch/arm/mach-orion/pci.c @@ -35,7 +35,7 @@ ****************************************************************************/ #define PCIE_BASE ((void __iomem *)ORION_PCIE_VIRT_BASE) -void orion_pcie_id(u32 *dev, u32 *rev) +void __init orion_pcie_id(u32 *dev, u32 *rev) { *dev = orion_pcie_dev_id(PCIE_BASE); *rev = orion_pcie_rev(PCIE_BASE); @@ -136,7 +136,7 @@ struct pci_ops pcie_ops = { }; -static int pcie_setup(struct pci_sys_data *sys) +static int __init pcie_setup(struct pci_sys_data *sys) { struct resource *res; int dev; @@ -362,7 +362,7 @@ struct pci_ops pci_ops = { .write = orion_pci_wr_conf, }; -static void orion_pci_set_bus_nr(int nr) +static void __init orion_pci_set_bus_nr(int nr) { u32 p2p = orion_read(PCI_P2P_CONF); @@ -387,7 +387,7 @@ static void orion_pci_set_bus_nr(int nr) } } -static void orion_pci_master_slave_enable(void) +static void __init orion_pci_master_slave_enable(void) { int bus_nr, dev_nr, func, reg; u32 val; @@ -401,7 +401,7 @@ static void orion_pci_master_slave_enable(void) orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7); } -static void orion_setup_pci_wins(struct mbus_dram_target_info *dram) +static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) { u32 win_enable; int bus; @@ -461,7 +461,7 @@ static void orion_setup_pci_wins(struct mbus_dram_target_info *dram) orion_setbits(PCI_ADDR_DECODE_CTRL, 1); } -static int pci_setup(struct pci_sys_data *sys) +static int __init pci_setup(struct pci_sys_data *sys) { struct resource *res; @@ -519,7 +519,7 @@ static int pci_setup(struct pci_sys_data *sys) /***************************************************************************** * General PCIE + PCI ****************************************************************************/ -int orion_pci_sys_setup(int nr, struct pci_sys_data *sys) +int __init orion_pci_sys_setup(int nr, struct pci_sys_data *sys) { int ret = 0; @@ -534,7 +534,7 @@ int orion_pci_sys_setup(int nr, struct pci_sys_data *sys) return ret; } -struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) +struct pci_bus __init *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) { struct pci_bus *bus; -- GitLab From d50c60a87a95a42f1bc984150d3eebc77a0b0c14 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:41 -0400 Subject: [PATCH 023/212] Orion: enable access to local config space This patch enables access to the local PCIe/PCI configuration space, and is necessary for such things as PCI Advanced Error Recovery to work. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/pci.c | 58 ++++++++++++++++++++++----------------- 1 file changed, 33 insertions(+), 25 deletions(-) diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c index 18cdf3b505a..e3aab14b943 100644 --- a/arch/arm/mach-orion/pci.c +++ b/arch/arm/mach-orion/pci.c @@ -50,15 +50,18 @@ static int pcie_valid_config(int bus, int dev) { /* * Don't go out when trying to access -- - * 1. our own device / nonexisting device on local bus + * 1. nonexisting device on local bus * 2. where there's no device connected (no link) */ - if (bus == 0 && dev != 1) - return 0; + if (bus == 0 && dev == 0) + return 1; if (!orion_pcie_link_up(PCIE_BASE)) return 0; + if (bus == 0 && dev != 1) + return 0; + return 1; } @@ -272,12 +275,6 @@ int orion_pci_local_bus_nr(void) return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); } -static int orion_pci_local_dev_nr(void) -{ - u32 conf = orion_read(PCI_P2P_CONF); - return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS); -} - static int orion_pci_hw_rd_conf(int bus, int dev, u32 func, u32 where, u32 size, u32 *val) { @@ -333,8 +330,8 @@ static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn, /* * Don't go out for local device */ - if ((orion_pci_local_bus_nr() == bus->number) && - (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) { + if (bus->number == orion_pci_local_bus_nr() && + PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) { *val = 0xffffffff; return PCIBIOS_DEVICE_NOT_FOUND; } @@ -346,11 +343,8 @@ static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn, static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - /* - * Don't go out for local device - */ - if ((orion_pci_local_bus_nr() == bus->number) && - (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) + if (bus->number == orion_pci_local_bus_nr() && + PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) return PCIBIOS_DEVICE_NOT_FOUND; return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), @@ -389,23 +383,21 @@ static void __init orion_pci_set_bus_nr(int nr) static void __init orion_pci_master_slave_enable(void) { - int bus_nr, dev_nr, func, reg; + int bus_nr, func, reg; u32 val; bus_nr = orion_pci_local_bus_nr(); - dev_nr = orion_pci_local_dev_nr(); func = PCI_CONF_FUNC_STAT_CMD; reg = PCI_CONF_REG_STAT_CMD; - orion_pci_hw_rd_conf(bus_nr, dev_nr, func, reg, 4, &val); + orion_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7); + orion_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); } static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) { u32 win_enable; int bus; - int dev; int i; /* @@ -418,7 +410,6 @@ static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) * Setup windows for DDR banks. */ bus = orion_pci_local_bus_nr(); - dev = orion_pci_local_dev_nr(); for (i = 0; i < dram->num_cs; i++) { struct mbus_dram_window *cs = dram->cs + i; @@ -430,15 +421,15 @@ static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) * Write DRAM bank base address register. */ reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); - orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val); + orion_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); val = (cs->base & 0xfffff000) | (val & 0xfff); - orion_pci_hw_wr_conf(bus, dev, func, reg, 4, val); + orion_pci_hw_wr_conf(bus, 0, func, reg, 4, val); /* * Write DRAM bank size register. */ reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); - orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0); + orion_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); orion_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), (cs->size - 1) & 0xfffff000); orion_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), @@ -519,6 +510,23 @@ static int __init pci_setup(struct pci_sys_data *sys) /***************************************************************************** * General PCIE + PCI ****************************************************************************/ +static void __devinit rc_pci_fixup(struct pci_dev *dev) +{ + /* + * Prevent enumeration of root complex. + */ + if (dev->bus->parent == NULL && dev->devfn == 0) { + int i; + + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { + dev->resource[i].start = 0; + dev->resource[i].end = 0; + dev->resource[i].flags = 0; + } + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); + int __init orion_pci_sys_setup(int nr, struct pci_sys_data *sys) { int ret = 0; -- GitLab From 159ffb3a04f6bc619643af680df406faafd0199d Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:41 -0400 Subject: [PATCH 024/212] Orion: general cleanup Various Orion cleanups: - Unify GPL license banner format across all files. - Unify naming of .h double inclusion guard preprocessor macros. - Unify spelling of "PCIe" (variants seen: PCIE, PCIe, PCI-EX.) - Various typo fixes. - Remove __init attributes from prototypes declared in headers. - Remove trailing comments from #endif statements. - Mark a couple of locally-used-only structs static. Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/mach-orion/addr-map.c | 8 +++--- arch/arm/mach-orion/common.c | 6 ++--- arch/arm/mach-orion/common.h | 19 +++++++------- arch/arm/mach-orion/db88f5281-setup.c | 4 +-- arch/arm/mach-orion/gpio.c | 4 +-- arch/arm/mach-orion/irq.c | 2 +- arch/arm/mach-orion/kurobox_pro-setup.c | 4 +-- arch/arm/mach-orion/pci.c | 32 ++++++++++++------------ arch/arm/mach-orion/rd88f5182-setup.c | 4 +-- include/asm-arm/arch-orion/debug-macro.S | 2 +- include/asm-arm/arch-orion/hardware.h | 4 +-- include/asm-arm/arch-orion/io.h | 8 +++--- include/asm-arm/arch-orion/irqs.h | 7 +++--- include/asm-arm/arch-orion/memory.h | 5 ++-- include/asm-arm/arch-orion/orion.h | 7 +++--- include/asm-arm/arch-orion/system.h | 5 ++-- include/asm-arm/arch-orion/timex.h | 4 +-- include/asm-arm/arch-orion/uncompress.h | 4 +-- 18 files changed, 66 insertions(+), 63 deletions(-) diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c index ecca987b57e..738de617e3c 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion/addr-map.c @@ -5,8 +5,8 @@ * * Maintainer: Tzachi Perelstein * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ @@ -45,9 +45,9 @@ * Generic Address Decode Windows bit settings */ #define TARGET_DDR 0 +#define TARGET_DEV_BUS 1 #define TARGET_PCI 3 #define TARGET_PCIE 4 -#define TARGET_DEV_BUS 1 #define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \ ((n) == 1) ? 0xd : \ ((n) == 2) ? 0xb : \ @@ -64,7 +64,7 @@ #define WIN_EN 1 /* - * Helpers to get DDR banks info + * Helpers to get DDR bank info */ #define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8)) #define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8)) diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index aae157d360e..85c8f18268a 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c @@ -5,8 +5,8 @@ * * Maintainer: Tzachi Perelstein * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ @@ -363,7 +363,7 @@ void __init orion_init(void) orion_setup_eth_wins(); /* - * REgister devices + * Register devices. */ platform_device_register(&orion_uart); platform_device_register(&orion_ehci0); diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h index 74f23e61c40..bcc31adaca1 100644 --- a/arch/arm/mach-orion/common.h +++ b/arch/arm/mach-orion/common.h @@ -1,13 +1,13 @@ -#ifndef __ARCH_ORION_COMMON_H__ -#define __ARCH_ORION_COMMON_H__ +#ifndef __ARCH_ORION_COMMON_H +#define __ARCH_ORION_COMMON_H /* * Basic Orion init functions used early by machine-setup. */ -void __init orion_map_io(void); -void __init orion_init_irq(void); -void __init orion_init(void); +void orion_map_io(void); +void orion_init_irq(void); +void orion_init(void); extern struct sys_timer orion_timer; /* @@ -43,7 +43,7 @@ struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); * (/mach-orion/gpio.c). */ -void __init orion_gpio_set_valid_pins(u32 pins); +void orion_gpio_set_valid_pins(u32 pins); void gpio_display(void); /* debug */ /* @@ -52,7 +52,7 @@ void gpio_display(void); /* debug */ struct mv643xx_eth_platform_data; -void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data); +void orion_eth_init(struct mv643xx_eth_platform_data *eth_data); /* * Orion Sata platform_data, used by machine-setup @@ -60,7 +60,7 @@ void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data); struct mv_sata_platform_data; -void __init orion_sata_init(struct mv_sata_platform_data *sata_data); +void orion_sata_init(struct mv_sata_platform_data *sata_data); struct machine_desc; struct meminfo; @@ -68,4 +68,5 @@ struct tag; extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *, char **, struct meminfo *); -#endif /* __ARCH_ORION_COMMON_H__ */ + +#endif diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion/db88f5281-setup.c index aad62efa1da..a0a9e4851b5 100644 --- a/arch/arm/mach-orion/db88f5281-setup.c +++ b/arch/arm/mach-orion/db88f5281-setup.c @@ -5,8 +5,8 @@ * * Maintainer: Tzachi Perelstein * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ diff --git a/arch/arm/mach-orion/gpio.c b/arch/arm/mach-orion/gpio.c index 5a7d9cc9b80..afc7be08b30 100644 --- a/arch/arm/mach-orion/gpio.c +++ b/arch/arm/mach-orion/gpio.c @@ -5,8 +5,8 @@ * * Maintainer: Tzachi Perelstein * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ diff --git a/arch/arm/mach-orion/irq.c b/arch/arm/mach-orion/irq.c index dc8cb15a817..7033cc1360e 100644 --- a/arch/arm/mach-orion/irq.c +++ b/arch/arm/mach-orion/irq.c @@ -6,7 +6,7 @@ * Maintainer: Tzachi Perelstein * * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion/kurobox_pro-setup.c index bf7034df8a6..be417e7f423 100644 --- a/arch/arm/mach-orion/kurobox_pro-setup.c +++ b/arch/arm/mach-orion/kurobox_pro-setup.c @@ -3,8 +3,8 @@ * * Maintainer: Ronen Shitrit * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c index e3aab14b943..59684cc329b 100644 --- a/arch/arm/mach-orion/pci.c +++ b/arch/arm/mach-orion/pci.c @@ -1,12 +1,12 @@ /* * arch/arm/mach-orion/pci.c * - * PCI and PCIE functions for Marvell Orion System On Chip + * PCI and PCIe functions for Marvell Orion System On Chip * * Maintainer: Tzachi Perelstein * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ @@ -18,12 +18,12 @@ #include "common.h" /***************************************************************************** - * Orion has one PCIE controller and one PCI controller. + * Orion has one PCIe controller and one PCI controller. * - * Note1: The local PCIE bus number is '0'. The local PCI bus number - * follows the scanned PCIE bridged busses, if any. + * Note1: The local PCIe bus number is '0'. The local PCI bus number + * follows the scanned PCIe bridged busses, if any. * - * Note2: It is possible for PCI/PCIE agents to access many subsystem's + * Note2: It is possible for PCI/PCIe agents to access many subsystem's * space, by configuring BARs and Address Decode Windows, e.g. flashes on * device bus, Orion registers, etc. However this code only enable the * access to DDR banks. @@ -31,7 +31,7 @@ /***************************************************************************** - * PCIE controller + * PCIe controller ****************************************************************************/ #define PCIE_BASE ((void __iomem *)ORION_PCIE_VIRT_BASE) @@ -67,7 +67,7 @@ static int pcie_valid_config(int bus, int dev) /* - * PCIE config cycles are done by programming the PCIE_CONF_ADDR register + * PCIe config cycles are done by programming the PCIE_CONF_ADDR register * and then reading the PCIE_CONF_DATA register. Need to make sure these * transactions are atomic. */ @@ -133,7 +133,7 @@ static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, return ret; } -struct pci_ops pcie_ops = { +static struct pci_ops pcie_ops = { .read = pcie_rd_conf, .write = pcie_wr_conf, }; @@ -170,23 +170,23 @@ static int __init pcie_setup(struct pci_sys_data *sys) /* * IORESOURCE_IO */ - res[0].name = "PCI-EX I/O Space"; + res[0].name = "PCIe I/O Space"; res[0].flags = IORESOURCE_IO; res[0].start = ORION_PCIE_IO_BUS_BASE; res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1; if (request_resource(&ioport_resource, &res[0])) - panic("Request PCIE IO resource failed\n"); + panic("Request PCIe IO resource failed\n"); sys->resource[0] = &res[0]; /* * IORESOURCE_MEM */ - res[1].name = "PCI-EX Memory Space"; + res[1].name = "PCIe Memory Space"; res[1].flags = IORESOURCE_MEM; res[1].start = ORION_PCIE_MEM_PHYS_BASE; res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1; if (request_resource(&iomem_resource, &res[1])) - panic("Request PCIE Memory resource failed\n"); + panic("Request PCIe Memory resource failed\n"); sys->resource[1] = &res[1]; sys->resource[2] = NULL; @@ -351,7 +351,7 @@ static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn, PCI_FUNC(devfn), where, size, val); } -struct pci_ops pci_ops = { +static struct pci_ops pci_ops = { .read = orion_pci_rd_conf, .write = orion_pci_wr_conf, }; @@ -508,7 +508,7 @@ static int __init pci_setup(struct pci_sys_data *sys) /***************************************************************************** - * General PCIE + PCI + * General PCIe + PCI ****************************************************************************/ static void __devinit rc_pci_fixup(struct pci_dev *dev) { diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion/rd88f5182-setup.c index 662c097ca33..f3e38ecda1c 100644 --- a/arch/arm/mach-orion/rd88f5182-setup.c +++ b/arch/arm/mach-orion/rd88f5182-setup.c @@ -5,8 +5,8 @@ * * Maintainer: Ronen Shitrit * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion/debug-macro.S index 2746220f5d8..c847f8c9250 100644 --- a/include/asm-arm/arch-orion/debug-macro.S +++ b/include/asm-arm/arch-orion/debug-macro.S @@ -1,5 +1,5 @@ /* - * linux/include/asm-arm/arch-orion/debug-macro.S + * include/asm-arm/arch-orion/debug-macro.S * * Debugging macro include header * diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion/hardware.h index 65da374de73..998af6029c7 100644 --- a/include/asm-arm/arch-orion/hardware.h +++ b/include/asm-arm/arch-orion/hardware.h @@ -6,8 +6,8 @@ * published by the Free Software Foundation. */ -#ifndef __ASM_ARCH_HARDWARE_H__ -#define __ASM_ARCH_HARDWARE_H__ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H #include "orion.h" diff --git a/include/asm-arm/arch-orion/io.h b/include/asm-arm/arch-orion/io.h index 486dc04d764..23820153b61 100644 --- a/include/asm-arm/arch-orion/io.h +++ b/include/asm-arm/arch-orion/io.h @@ -3,13 +3,13 @@ * * Tzachi Perelstein * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H #include "orion.h" diff --git a/include/asm-arm/arch-orion/irqs.h b/include/asm-arm/arch-orion/irqs.h index eea65ca6076..70a2420456a 100644 --- a/include/asm-arm/arch-orion/irqs.h +++ b/include/asm-arm/arch-orion/irqs.h @@ -10,8 +10,8 @@ * warranty of any kind, whether express or implied. */ -#ifndef __ASM_ARCH_IRQS_H__ -#define __ASM_ARCH_IRQS_H__ +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H #include "orion.h" /* need GPIO_MAX */ @@ -58,4 +58,5 @@ #define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS) -#endif /* __ASM_ARCH_IRQS_H__ */ + +#endif diff --git a/include/asm-arm/arch-orion/memory.h b/include/asm-arm/arch-orion/memory.h index d954dba87ce..d9300d62a53 100644 --- a/include/asm-arm/arch-orion/memory.h +++ b/include/asm-arm/arch-orion/memory.h @@ -4,12 +4,13 @@ * Marvell Orion memory definitions */ -#ifndef __ASM_ARCH_MMU_H -#define __ASM_ARCH_MMU_H +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H #define PHYS_OFFSET UL(0x00000000) #define __virt_to_bus(x) __virt_to_phys(x) #define __bus_to_virt(x) __phys_to_virt(x) + #endif diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h index d0b32c379ae..01f1299472d 100644 --- a/include/asm-arm/arch-orion/orion.h +++ b/include/asm-arm/arch-orion/orion.h @@ -11,8 +11,8 @@ * warranty of any kind, whether express or implied. */ -#ifndef __ASM_ARCH_ORION_H__ -#define __ASM_ARCH_ORION_H__ +#ifndef __ASM_ARCH_ORION_H +#define __ASM_ARCH_ORION_H /***************************************************************************** * Orion Address Maps @@ -91,6 +91,7 @@ #define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000) #define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x)) +#define TIMER_VIRT_BASE (ORION_BRIDGE_VIRT_BASE | 0x300) #define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000) #define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x)) @@ -154,7 +155,5 @@ #define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200) #define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204) -#define TIMER_VIRT_BASE (ORION_BRIDGE_VIRT_BASE | 0x300) - #endif diff --git a/include/asm-arm/arch-orion/system.h b/include/asm-arm/arch-orion/system.h index 17704c68f90..653f992bbe6 100644 --- a/include/asm-arm/arch-orion/system.h +++ b/include/asm-arm/arch-orion/system.h @@ -3,8 +3,8 @@ * * Tzachi Perelstein * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ @@ -28,4 +28,5 @@ static inline void arch_reset(char mode) orion_setbits(CPU_SOFT_RESET, 1); } + #endif diff --git a/include/asm-arm/arch-orion/timex.h b/include/asm-arm/arch-orion/timex.h index cc0fc7075eb..85588d9c22e 100644 --- a/include/asm-arm/arch-orion/timex.h +++ b/include/asm-arm/arch-orion/timex.h @@ -3,8 +3,8 @@ * * Tzachi Perelstein * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion/uncompress.h index 59f44039909..03306cdd51b 100644 --- a/include/asm-arm/arch-orion/uncompress.h +++ b/include/asm-arm/arch-orion/uncompress.h @@ -3,8 +3,8 @@ * * Tzachi Perelstein * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -- GitLab From 9dd0b194bf6804b1998f0fe261b2606ec7b58d72 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 27 Mar 2008 14:51:41 -0400 Subject: [PATCH 025/212] Orion: orion -> orion5x rename Do a global s/orion/orion5x/ of the Orion 5x-specific bits (i.e. not the plat-orion bits.) Signed-off-by: Lennert Buytenhek Reviewed-by: Tzachi Perelstein Acked-by: Saeed Bishara Acked-by: Russell King Signed-off-by: Nicolas Pitre --- arch/arm/Kconfig | 7 +- arch/arm/Makefile | 2 +- .../{orion_defconfig => orion5x_defconfig} | 2 +- arch/arm/mach-orion/common.h | 72 ------- arch/arm/{mach-orion => mach-orion5x}/Kconfig | 2 +- .../arm/{mach-orion => mach-orion5x}/Makefile | 0 .../Makefile.boot | 0 .../{mach-orion => mach-orion5x}/addr-map.c | 108 +++++----- .../arm/{mach-orion => mach-orion5x}/common.c | 202 +++++++++--------- arch/arm/mach-orion5x/common.h | 72 +++++++ .../db88f5281-setup.c | 44 ++-- .../dns323-setup.c | 41 ++-- arch/arm/{mach-orion => mach-orion5x}/gpio.c | 72 +++---- arch/arm/{mach-orion => mach-orion5x}/irq.c | 94 ++++---- .../kurobox_pro-setup.c | 43 ++-- arch/arm/{mach-orion => mach-orion5x}/pci.c | 160 +++++++------- .../rd88f5182-setup.c | 43 ++-- .../ts209-setup.c | 57 ++--- arch/arm/mm/Kconfig | 2 +- include/asm-arm/arch-orion/irqs.h | 62 ------ include/asm-arm/arch-orion/orion.h | 159 -------------- .../debug-macro.S | 8 +- .../{arch-orion => arch-orion5x}/dma.h | 0 .../entry-macro.S | 4 +- .../{arch-orion => arch-orion5x}/gpio.h | 8 +- .../{arch-orion => arch-orion5x}/hardware.h | 6 +- .../asm-arm/{arch-orion => arch-orion5x}/io.h | 26 +-- include/asm-arm/arch-orion5x/irqs.h | 62 ++++++ .../{arch-orion => arch-orion5x}/memory.h | 2 +- include/asm-arm/arch-orion5x/orion5x.h | 159 ++++++++++++++ .../{arch-orion => arch-orion5x}/system.h | 8 +- .../{arch-orion => arch-orion5x}/timex.h | 4 +- .../{arch-orion => arch-orion5x}/uncompress.h | 4 +- .../{arch-orion => arch-orion5x}/vmalloc.h | 2 +- 34 files changed, 771 insertions(+), 766 deletions(-) rename arch/arm/configs/{orion_defconfig => orion5x_defconfig} (99%) delete mode 100644 arch/arm/mach-orion/common.h rename arch/arm/{mach-orion => mach-orion5x}/Kconfig (98%) rename arch/arm/{mach-orion => mach-orion5x}/Makefile (100%) rename arch/arm/{mach-orion => mach-orion5x}/Makefile.boot (100%) rename arch/arm/{mach-orion => mach-orion5x}/addr-map.c (59%) rename arch/arm/{mach-orion => mach-orion5x}/common.c (57%) create mode 100644 arch/arm/mach-orion5x/common.h rename arch/arm/{mach-orion => mach-orion5x}/db88f5281-setup.c (90%) rename arch/arm/{mach-orion => mach-orion5x}/dns323-setup.c (90%) rename arch/arm/{mach-orion => mach-orion5x}/gpio.c (71%) rename arch/arm/{mach-orion => mach-orion5x}/irq.c (62%) rename arch/arm/{mach-orion => mach-orion5x}/kurobox_pro-setup.c (86%) rename arch/arm/{mach-orion => mach-orion5x}/pci.c (71%) rename arch/arm/{mach-orion => mach-orion5x}/rd88f5182-setup.c (89%) rename arch/arm/{mach-orion => mach-orion5x}/ts209-setup.c (88%) delete mode 100644 include/asm-arm/arch-orion/irqs.h delete mode 100644 include/asm-arm/arch-orion/orion.h rename include/asm-arm/{arch-orion => arch-orion5x}/debug-macro.S (73%) rename include/asm-arm/{arch-orion => arch-orion5x}/dma.h (100%) rename include/asm-arm/{arch-orion => arch-orion5x}/entry-macro.S (90%) rename include/asm-arm/{arch-orion => arch-orion5x}/gpio.h (79%) rename include/asm-arm/{arch-orion => arch-orion5x}/hardware.h (77%) rename include/asm-arm/{arch-orion => arch-orion5x}/io.h (61%) create mode 100644 include/asm-arm/arch-orion5x/irqs.h rename include/asm-arm/{arch-orion => arch-orion5x}/memory.h (85%) create mode 100644 include/asm-arm/arch-orion5x/orion5x.h rename include/asm-arm/{arch-orion => arch-orion5x}/system.h (76%) rename include/asm-arm/{arch-orion => arch-orion5x}/timex.h (79%) rename include/asm-arm/{arch-orion => arch-orion5x}/uncompress.h (89%) rename include/asm-arm/{arch-orion => arch-orion5x}/vmalloc.h (51%) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 845f96e9f0d..2f4fb773f3e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -377,7 +377,7 @@ config ARCH_MXC help Support for Freescale MXC/iMX-based family of processors -config ARCH_ORION +config ARCH_ORION5X bool "Marvell Orion" depends on MMU select PCI @@ -386,7 +386,8 @@ config ARCH_ORION select GENERIC_CLOCKEVENTS select PLAT_ORION help - Support for Marvell Orion System on Chip family. + Support for the following Marvell Orion 5x series SoCs: + Orion-1 (5181), Orion-NAS (5182), Orion-2 (5281.) config ARCH_PNX4008 bool "Philips Nexperia PNX4008 Mobile" @@ -517,7 +518,7 @@ source "arch/arm/mach-omap1/Kconfig" source "arch/arm/mach-omap2/Kconfig" -source "arch/arm/mach-orion/Kconfig" +source "arch/arm/mach-orion5x/Kconfig" source "arch/arm/plat-s3c24xx/Kconfig" source "arch/arm/plat-s3c/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 27866cf0c18..6f997505375 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -139,7 +139,7 @@ endif machine-$(CONFIG_ARCH_KS8695) := ks8695 incdir-$(CONFIG_ARCH_MXC) := mxc machine-$(CONFIG_ARCH_MX3) := mx3 - machine-$(CONFIG_ARCH_ORION) := orion + machine-$(CONFIG_ARCH_ORION5X) := orion5x machine-$(CONFIG_ARCH_MSM7X00A) := msm ifeq ($(CONFIG_ARCH_EBSA110),y) diff --git a/arch/arm/configs/orion_defconfig b/arch/arm/configs/orion5x_defconfig similarity index 99% rename from arch/arm/configs/orion_defconfig rename to arch/arm/configs/orion5x_defconfig index 1e5aaa645fc..52cd99bd52f 100644 --- a/arch/arm/configs/orion_defconfig +++ b/arch/arm/configs/orion5x_defconfig @@ -140,7 +140,7 @@ CONFIG_CLASSIC_RCU=y # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_MXC is not set -CONFIG_ARCH_ORION=y +CONFIG_ARCH_ORION5X=y # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_RPC is not set diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h deleted file mode 100644 index bcc31adaca1..00000000000 --- a/arch/arm/mach-orion/common.h +++ /dev/null @@ -1,72 +0,0 @@ -#ifndef __ARCH_ORION_COMMON_H -#define __ARCH_ORION_COMMON_H - -/* - * Basic Orion init functions used early by machine-setup. - */ - -void orion_map_io(void); -void orion_init_irq(void); -void orion_init(void); -extern struct sys_timer orion_timer; - -/* - * Enumerations and functions for Orion windows mapping. Used by Orion core - * functions to map its interfaces and by the machine-setup to map its on- - * board devices. Details in /mach-orion/addr-map.c - */ -extern struct mbus_dram_target_info orion_mbus_dram_info; -void orion_setup_cpu_mbus_bridge(void); -void orion_setup_dev_boot_win(u32 base, u32 size); -void orion_setup_dev0_win(u32 base, u32 size); -void orion_setup_dev1_win(u32 base, u32 size); -void orion_setup_dev2_win(u32 base, u32 size); -void orion_setup_pcie_wa_win(u32 base, u32 size); -void orion_setup_eth_wins(void); - -/* - * Shared code used internally by other Orion core functions. - * (/mach-orion/pci.c) - */ - -struct pci_sys_data; -struct pci_bus; - -void orion_pcie_id(u32 *dev, u32 *rev); -int orion_pcie_local_bus_nr(void); -int orion_pci_local_bus_nr(void); -int orion_pci_sys_setup(int nr, struct pci_sys_data *sys); -struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); - -/* - * Valid GPIO pins according to MPP setup, used by machine-setup. - * (/mach-orion/gpio.c). - */ - -void orion_gpio_set_valid_pins(u32 pins); -void gpio_display(void); /* debug */ - -/* - * Pull in Orion Ethernet platform_data, used by machine-setup - */ - -struct mv643xx_eth_platform_data; - -void orion_eth_init(struct mv643xx_eth_platform_data *eth_data); - -/* - * Orion Sata platform_data, used by machine-setup - */ - -struct mv_sata_platform_data; - -void orion_sata_init(struct mv_sata_platform_data *sata_data); - -struct machine_desc; -struct meminfo; -struct tag; -extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *, - char **, struct meminfo *); - - -#endif diff --git a/arch/arm/mach-orion/Kconfig b/arch/arm/mach-orion5x/Kconfig similarity index 98% rename from arch/arm/mach-orion/Kconfig rename to arch/arm/mach-orion5x/Kconfig index 1dcbb6ac5a3..01c66957d8f 100644 --- a/arch/arm/mach-orion/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -1,4 +1,4 @@ -if ARCH_ORION +if ARCH_ORION5X menu "Orion Implementations" diff --git a/arch/arm/mach-orion/Makefile b/arch/arm/mach-orion5x/Makefile similarity index 100% rename from arch/arm/mach-orion/Makefile rename to arch/arm/mach-orion5x/Makefile diff --git a/arch/arm/mach-orion/Makefile.boot b/arch/arm/mach-orion5x/Makefile.boot similarity index 100% rename from arch/arm/mach-orion/Makefile.boot rename to arch/arm/mach-orion5x/Makefile.boot diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion5x/addr-map.c similarity index 59% rename from arch/arm/mach-orion/addr-map.c rename to arch/arm/mach-orion5x/addr-map.c index 738de617e3c..6b179371e0a 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c @@ -1,7 +1,7 @@ /* - * arch/arm/mach-orion/addr-map.c + * arch/arm/mach-orion5x/addr-map.c * - * Address map functions for Marvell Orion System On Chip + * Address map functions for Marvell Orion 5x SoCs * * Maintainer: Tzachi Perelstein * @@ -29,7 +29,7 @@ * Setup access to PCI and PCI-E IO/MEM space is issued by this file. * Setup access to various devices located on the device bus interface (e.g. * flashes, RTC, etc) should be issued by machine-setup.c according to - * specific board population (by using orion_setup_*_win()). + * specific board population (by using orion5x_setup_*_win()). * * Non-CPU Masters address decoding -- * Unlike the CPU, we setup the access from Orion's master interfaces to DDR @@ -66,8 +66,8 @@ /* * Helpers to get DDR bank info */ -#define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8)) -#define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8)) +#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) * 8)) +#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) * 8)) #define DDR_MAX_CS 4 #define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1) #define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000) @@ -76,30 +76,30 @@ /* * CPU Address Decode Windows registers */ -#define CPU_WIN_CTRL(n) ORION_BRIDGE_REG(0x000 | ((n) << 4)) -#define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4)) -#define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4)) -#define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4)) +#define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4)) +#define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4)) +#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4)) +#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4)) /* * Gigabit Ethernet Address Decode Windows registers */ -#define ETH_WIN_BASE(win) ORION_ETH_REG(0x200 + ((win) * 8)) -#define ETH_WIN_SIZE(win) ORION_ETH_REG(0x204 + ((win) * 8)) -#define ETH_WIN_REMAP(win) ORION_ETH_REG(0x280 + ((win) * 4)) -#define ETH_WIN_EN ORION_ETH_REG(0x290) -#define ETH_WIN_PROT ORION_ETH_REG(0x294) +#define ETH_WIN_BASE(win) ORION5X_ETH_REG(0x200 + ((win) * 8)) +#define ETH_WIN_SIZE(win) ORION5X_ETH_REG(0x204 + ((win) * 8)) +#define ETH_WIN_REMAP(win) ORION5X_ETH_REG(0x280 + ((win) * 4)) +#define ETH_WIN_EN ORION5X_ETH_REG(0x290) +#define ETH_WIN_PROT ORION5X_ETH_REG(0x294) #define ETH_MAX_WIN 6 #define ETH_MAX_REMAP_WIN 4 -struct mbus_dram_target_info orion_mbus_dram_info; +struct mbus_dram_target_info orion5x_mbus_dram_info; -static int __init orion_cpu_win_can_remap(int win) +static int __init orion5x_cpu_win_can_remap(int win) { u32 dev, rev; - orion_pcie_id(&dev, &rev); + orion5x_pcie_id(&dev, &rev); if ((dev == MV88F5281_DEV_ID && win < 4) || (dev == MV88F5182_DEV_ID && win < 2) || (dev == MV88F5181_DEV_ID && win < 2)) @@ -111,20 +111,20 @@ static int __init orion_cpu_win_can_remap(int win) static void __init setup_cpu_win(int win, u32 base, u32 size, u8 target, u8 attr, int remap) { - orion_write(CPU_WIN_BASE(win), base & 0xffff0000); - orion_write(CPU_WIN_CTRL(win), + orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000); + orion5x_write(CPU_WIN_CTRL(win), ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1); - if (orion_cpu_win_can_remap(win)) { + if (orion5x_cpu_win_can_remap(win)) { if (remap < 0) remap = base; - orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); - orion_write(CPU_WIN_REMAP_HI(win), 0); + orion5x_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); + orion5x_write(CPU_WIN_REMAP_HI(win), 0); } } -void __init orion_setup_cpu_mbus_bridge(void) +void __init orion5x_setup_cpu_mbus_bridge(void) { int i; int cs; @@ -133,30 +133,30 @@ void __init orion_setup_cpu_mbus_bridge(void) * First, disable and clear windows. */ for (i = 0; i < 8; i++) { - orion_write(CPU_WIN_BASE(i), 0); - orion_write(CPU_WIN_CTRL(i), 0); - if (orion_cpu_win_can_remap(i)) { - orion_write(CPU_WIN_REMAP_LO(i), 0); - orion_write(CPU_WIN_REMAP_HI(i), 0); + orion5x_write(CPU_WIN_BASE(i), 0); + orion5x_write(CPU_WIN_CTRL(i), 0); + if (orion5x_cpu_win_can_remap(i)) { + orion5x_write(CPU_WIN_REMAP_LO(i), 0); + orion5x_write(CPU_WIN_REMAP_HI(i), 0); } } /* * Setup windows for PCI+PCIe IO+MEM space. */ - setup_cpu_win(0, ORION_PCIE_IO_PHYS_BASE, ORION_PCIE_IO_SIZE, - TARGET_PCIE, ATTR_PCIE_IO, ORION_PCIE_IO_BUS_BASE); - setup_cpu_win(1, ORION_PCI_IO_PHYS_BASE, ORION_PCI_IO_SIZE, - TARGET_PCI, ATTR_PCI_IO, ORION_PCI_IO_BUS_BASE); - setup_cpu_win(2, ORION_PCIE_MEM_PHYS_BASE, ORION_PCIE_MEM_SIZE, + setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, + TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE); + setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, + TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE); + setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE, TARGET_PCIE, ATTR_PCIE_MEM, -1); - setup_cpu_win(3, ORION_PCI_MEM_PHYS_BASE, ORION_PCI_MEM_SIZE, + setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, TARGET_PCI, ATTR_PCI_MEM, -1); /* * Setup MBUS dram target info. */ - orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; for (i = 0, cs = 0; i < 4; i++) { u32 base = readl(DDR_BASE_CS(i)); @@ -168,42 +168,42 @@ void __init orion_setup_cpu_mbus_bridge(void) if (size & 1) { struct mbus_dram_window *w; - w = &orion_mbus_dram_info.cs[cs++]; + w = &orion5x_mbus_dram_info.cs[cs++]; w->cs_index = i; w->mbus_attr = 0xf & ~(1 << i); w->base = base & 0xff000000; w->size = (size | 0x00ffffff) + 1; } } - orion_mbus_dram_info.num_cs = cs; + orion5x_mbus_dram_info.num_cs = cs; } -void __init orion_setup_dev_boot_win(u32 base, u32 size) +void __init orion5x_setup_dev_boot_win(u32 base, u32 size) { setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); } -void __init orion_setup_dev0_win(u32 base, u32 size) +void __init orion5x_setup_dev0_win(u32 base, u32 size) { setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1); } -void __init orion_setup_dev1_win(u32 base, u32 size) +void __init orion5x_setup_dev1_win(u32 base, u32 size) { setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1); } -void __init orion_setup_dev2_win(u32 base, u32 size) +void __init orion5x_setup_dev2_win(u32 base, u32 size) { setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1); } -void __init orion_setup_pcie_wa_win(u32 base, u32 size) +void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) { setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); } -void __init orion_setup_eth_wins(void) +void __init orion5x_setup_eth_wins(void) { int i; @@ -211,12 +211,12 @@ void __init orion_setup_eth_wins(void) * First, disable and clear windows */ for (i = 0; i < ETH_MAX_WIN; i++) { - orion_write(ETH_WIN_BASE(i), 0); - orion_write(ETH_WIN_SIZE(i), 0); - orion_setbits(ETH_WIN_EN, 1 << i); - orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2)); + orion5x_write(ETH_WIN_BASE(i), 0); + orion5x_write(ETH_WIN_SIZE(i), 0); + orion5x_setbits(ETH_WIN_EN, 1 << i); + orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2)); if (i < ETH_MAX_REMAP_WIN) - orion_write(ETH_WIN_REMAP(i), 0); + orion5x_write(ETH_WIN_REMAP(i), 0); } /* @@ -224,17 +224,17 @@ void __init orion_setup_eth_wins(void) */ for (i = 0; i < DDR_MAX_CS; i++) { u32 base, size; - size = orion_read(DDR_SIZE_CS(i)); - base = orion_read(DDR_BASE_CS(i)); + size = orion5x_read(DDR_SIZE_CS(i)); + base = orion5x_read(DDR_BASE_CS(i)); if (size & DDR_BANK_EN) { base = DDR_REG_TO_BASE(base); size = DDR_REG_TO_SIZE(size); - orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000); - orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) | + orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000); + orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) | (ATTR_DDR_CS(i) << 8) | TARGET_DDR); - orion_clrbits(ETH_WIN_EN, 1 << i); - orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2)); + orion5x_clrbits(ETH_WIN_EN, 1 << i); + orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2)); } } } diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion5x/common.c similarity index 57% rename from arch/arm/mach-orion/common.c rename to arch/arm/mach-orion5x/common.c index 85c8f18268a..439c7784af0 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -1,7 +1,7 @@ /* - * arch/arm/mach-orion/common.c + * arch/arm/mach-orion5x/common.c * - * Core functions for Marvell Orion System On Chip + * Core functions for Marvell Orion 5x SoCs * * Maintainer: Tzachi Perelstein * @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include @@ -34,51 +34,51 @@ /***************************************************************************** * I/O Address Mapping ****************************************************************************/ -static struct map_desc orion_io_desc[] __initdata = { +static struct map_desc orion5x_io_desc[] __initdata = { { - .virtual = ORION_REGS_VIRT_BASE, - .pfn = __phys_to_pfn(ORION_REGS_PHYS_BASE), - .length = ORION_REGS_SIZE, + .virtual = ORION5X_REGS_VIRT_BASE, + .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), + .length = ORION5X_REGS_SIZE, .type = MT_DEVICE }, { - .virtual = ORION_PCIE_IO_VIRT_BASE, - .pfn = __phys_to_pfn(ORION_PCIE_IO_PHYS_BASE), - .length = ORION_PCIE_IO_SIZE, + .virtual = ORION5X_PCIE_IO_VIRT_BASE, + .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), + .length = ORION5X_PCIE_IO_SIZE, .type = MT_DEVICE }, { - .virtual = ORION_PCI_IO_VIRT_BASE, - .pfn = __phys_to_pfn(ORION_PCI_IO_PHYS_BASE), - .length = ORION_PCI_IO_SIZE, + .virtual = ORION5X_PCI_IO_VIRT_BASE, + .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), + .length = ORION5X_PCI_IO_SIZE, .type = MT_DEVICE }, { - .virtual = ORION_PCIE_WA_VIRT_BASE, - .pfn = __phys_to_pfn(ORION_PCIE_WA_PHYS_BASE), - .length = ORION_PCIE_WA_SIZE, + .virtual = ORION5X_PCIE_WA_VIRT_BASE, + .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), + .length = ORION5X_PCIE_WA_SIZE, .type = MT_DEVICE }, }; -void __init orion_map_io(void) +void __init orion5x_map_io(void) { - iotable_init(orion_io_desc, ARRAY_SIZE(orion_io_desc)); + iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); } /***************************************************************************** * UART ****************************************************************************/ -static struct resource orion_uart_resources[] = { +static struct resource orion5x_uart_resources[] = { { .start = UART0_PHYS_BASE, .end = UART0_PHYS_BASE + 0xff, .flags = IORESOURCE_MEM, }, { - .start = IRQ_ORION_UART0, - .end = IRQ_ORION_UART0, + .start = IRQ_ORION5X_UART0, + .end = IRQ_ORION5X_UART0, .flags = IORESOURCE_IRQ, }, { @@ -87,102 +87,102 @@ static struct resource orion_uart_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = IRQ_ORION_UART1, - .end = IRQ_ORION_UART1, + .start = IRQ_ORION5X_UART1, + .end = IRQ_ORION5X_UART1, .flags = IORESOURCE_IRQ, }, }; -static struct plat_serial8250_port orion_uart_data[] = { +static struct plat_serial8250_port orion5x_uart_data[] = { { .mapbase = UART0_PHYS_BASE, .membase = (char *)UART0_VIRT_BASE, - .irq = IRQ_ORION_UART0, + .irq = IRQ_ORION5X_UART0, .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, .iotype = UPIO_MEM, .regshift = 2, - .uartclk = ORION_TCLK, + .uartclk = ORION5X_TCLK, }, { .mapbase = UART1_PHYS_BASE, .membase = (char *)UART1_VIRT_BASE, - .irq = IRQ_ORION_UART1, + .irq = IRQ_ORION5X_UART1, .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, .iotype = UPIO_MEM, .regshift = 2, - .uartclk = ORION_TCLK, + .uartclk = ORION5X_TCLK, }, { }, }; -static struct platform_device orion_uart = { +static struct platform_device orion5x_uart = { .name = "serial8250", .id = PLAT8250_DEV_PLATFORM, .dev = { - .platform_data = orion_uart_data, + .platform_data = orion5x_uart_data, }, - .resource = orion_uart_resources, - .num_resources = ARRAY_SIZE(orion_uart_resources), + .resource = orion5x_uart_resources, + .num_resources = ARRAY_SIZE(orion5x_uart_resources), }; /******************************************************************************* * USB Controller - 2 interfaces ******************************************************************************/ -static struct resource orion_ehci0_resources[] = { +static struct resource orion5x_ehci0_resources[] = { { - .start = ORION_USB0_PHYS_BASE, - .end = ORION_USB0_PHYS_BASE + SZ_4K, + .start = ORION5X_USB0_PHYS_BASE, + .end = ORION5X_USB0_PHYS_BASE + SZ_4K, .flags = IORESOURCE_MEM, }, { - .start = IRQ_ORION_USB0_CTRL, - .end = IRQ_ORION_USB0_CTRL, + .start = IRQ_ORION5X_USB0_CTRL, + .end = IRQ_ORION5X_USB0_CTRL, .flags = IORESOURCE_IRQ, }, }; -static struct resource orion_ehci1_resources[] = { +static struct resource orion5x_ehci1_resources[] = { { - .start = ORION_USB1_PHYS_BASE, - .end = ORION_USB1_PHYS_BASE + SZ_4K, + .start = ORION5X_USB1_PHYS_BASE, + .end = ORION5X_USB1_PHYS_BASE + SZ_4K, .flags = IORESOURCE_MEM, }, { - .start = IRQ_ORION_USB1_CTRL, - .end = IRQ_ORION_USB1_CTRL, + .start = IRQ_ORION5X_USB1_CTRL, + .end = IRQ_ORION5X_USB1_CTRL, .flags = IORESOURCE_IRQ, }, }; -static struct orion_ehci_data orion_ehci_data = { - .dram = &orion_mbus_dram_info, +static struct orion_ehci_data orion5x_ehci_data = { + .dram = &orion5x_mbus_dram_info, }; static u64 ehci_dmamask = 0xffffffffUL; -static struct platform_device orion_ehci0 = { +static struct platform_device orion5x_ehci0 = { .name = "orion-ehci", .id = 0, .dev = { .dma_mask = &ehci_dmamask, .coherent_dma_mask = 0xffffffff, - .platform_data = &orion_ehci_data, + .platform_data = &orion5x_ehci_data, }, - .resource = orion_ehci0_resources, - .num_resources = ARRAY_SIZE(orion_ehci0_resources), + .resource = orion5x_ehci0_resources, + .num_resources = ARRAY_SIZE(orion5x_ehci0_resources), }; -static struct platform_device orion_ehci1 = { +static struct platform_device orion5x_ehci1 = { .name = "orion-ehci", .id = 1, .dev = { .dma_mask = &ehci_dmamask, .coherent_dma_mask = 0xffffffff, - .platform_data = &orion_ehci_data, + .platform_data = &orion5x_ehci_data, }, - .resource = orion_ehci1_resources, - .num_resources = ARRAY_SIZE(orion_ehci1_resources), + .resource = orion5x_ehci1_resources, + .num_resources = ARRAY_SIZE(orion5x_ehci1_resources), }; /***************************************************************************** @@ -190,42 +190,42 @@ static struct platform_device orion_ehci1 = { * (The Orion and Discovery (MV643xx) families use the same Ethernet driver) ****************************************************************************/ -static struct resource orion_eth_shared_resources[] = { +static struct resource orion5x_eth_shared_resources[] = { { - .start = ORION_ETH_PHYS_BASE + 0x2000, - .end = ORION_ETH_PHYS_BASE + 0x3fff, + .start = ORION5X_ETH_PHYS_BASE + 0x2000, + .end = ORION5X_ETH_PHYS_BASE + 0x3fff, .flags = IORESOURCE_MEM, }, }; -static struct platform_device orion_eth_shared = { +static struct platform_device orion5x_eth_shared = { .name = MV643XX_ETH_SHARED_NAME, .id = 0, .num_resources = 1, - .resource = orion_eth_shared_resources, + .resource = orion5x_eth_shared_resources, }; -static struct resource orion_eth_resources[] = { +static struct resource orion5x_eth_resources[] = { { .name = "eth irq", - .start = IRQ_ORION_ETH_SUM, - .end = IRQ_ORION_ETH_SUM, + .start = IRQ_ORION5X_ETH_SUM, + .end = IRQ_ORION5X_ETH_SUM, .flags = IORESOURCE_IRQ, } }; -static struct platform_device orion_eth = { +static struct platform_device orion5x_eth = { .name = MV643XX_ETH_NAME, .id = 0, .num_resources = 1, - .resource = orion_eth_resources, + .resource = orion5x_eth_resources, }; -void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data) +void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) { - orion_eth.dev.platform_data = eth_data; - platform_device_register(&orion_eth_shared); - platform_device_register(&orion_eth); + orion5x_eth.dev.platform_data = eth_data; + platform_device_register(&orion5x_eth_shared); + platform_device_register(&orion5x_eth); } /***************************************************************************** @@ -233,13 +233,13 @@ void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data) * (The Orion and Discovery (MV643xx) families share the same I2C controller) ****************************************************************************/ -static struct mv64xxx_i2c_pdata orion_i2c_pdata = { +static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = { .freq_m = 8, /* assumes 166 MHz TCLK */ .freq_n = 3, .timeout = 1000, /* Default timeout of 1 second */ }; -static struct resource orion_i2c_resources[] = { +static struct resource orion5x_i2c_resources[] = { { .name = "i2c base", .start = I2C_PHYS_BASE, @@ -248,68 +248,68 @@ static struct resource orion_i2c_resources[] = { }, { .name = "i2c irq", - .start = IRQ_ORION_I2C, - .end = IRQ_ORION_I2C, + .start = IRQ_ORION5X_I2C, + .end = IRQ_ORION5X_I2C, .flags = IORESOURCE_IRQ, }, }; -static struct platform_device orion_i2c = { +static struct platform_device orion5x_i2c = { .name = MV64XXX_I2C_CTLR_NAME, .id = 0, - .num_resources = ARRAY_SIZE(orion_i2c_resources), - .resource = orion_i2c_resources, + .num_resources = ARRAY_SIZE(orion5x_i2c_resources), + .resource = orion5x_i2c_resources, .dev = { - .platform_data = &orion_i2c_pdata, + .platform_data = &orion5x_i2c_pdata, }, }; /***************************************************************************** * Sata port ****************************************************************************/ -static struct resource orion_sata_resources[] = { +static struct resource orion5x_sata_resources[] = { { .name = "sata base", - .start = ORION_SATA_PHYS_BASE, - .end = ORION_SATA_PHYS_BASE + 0x5000 - 1, + .start = ORION5X_SATA_PHYS_BASE, + .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1, .flags = IORESOURCE_MEM, }, { .name = "sata irq", - .start = IRQ_ORION_SATA, - .end = IRQ_ORION_SATA, + .start = IRQ_ORION5X_SATA, + .end = IRQ_ORION5X_SATA, .flags = IORESOURCE_IRQ, }, }; -static struct platform_device orion_sata = { +static struct platform_device orion5x_sata = { .name = "sata_mv", .id = 0, .dev = { .coherent_dma_mask = 0xffffffff, }, - .num_resources = ARRAY_SIZE(orion_sata_resources), - .resource = orion_sata_resources, + .num_resources = ARRAY_SIZE(orion5x_sata_resources), + .resource = orion5x_sata_resources, }; -void __init orion_sata_init(struct mv_sata_platform_data *sata_data) +void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) { - sata_data->dram = &orion_mbus_dram_info; - orion_sata.dev.platform_data = sata_data; - platform_device_register(&orion_sata); + sata_data->dram = &orion5x_mbus_dram_info; + orion5x_sata.dev.platform_data = sata_data; + platform_device_register(&orion5x_sata); } /***************************************************************************** * Time handling ****************************************************************************/ -static void orion_timer_init(void) +static void orion5x_timer_init(void) { - orion_time_init(IRQ_ORION_BRIDGE, ORION_TCLK); + orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK); } -struct sys_timer orion_timer = { - .init = orion_timer_init, +struct sys_timer orion5x_timer = { + .init = orion5x_timer_init, }; /***************************************************************************** @@ -319,9 +319,9 @@ struct sys_timer orion_timer = { /* * Identify device ID and rev from PCIE configuration header space '0'. */ -static void __init orion_id(u32 *dev, u32 *rev, char **dev_name) +static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) { - orion_pcie_id(dev, rev); + orion5x_pcie_id(dev, rev); if (*dev == MV88F5281_DEV_ID) { if (*rev == MV88F5281_REV_D2) { @@ -348,28 +348,28 @@ static void __init orion_id(u32 *dev, u32 *rev, char **dev_name) } } -void __init orion_init(void) +void __init orion5x_init(void) { char *dev_name; u32 dev, rev; - orion_id(&dev, &rev, &dev_name); - printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION_TCLK); + orion5x_id(&dev, &rev, &dev_name); + printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION5X_TCLK); /* * Setup Orion address map */ - orion_setup_cpu_mbus_bridge(); - orion_setup_eth_wins(); + orion5x_setup_cpu_mbus_bridge(); + orion5x_setup_eth_wins(); /* * Register devices. */ - platform_device_register(&orion_uart); - platform_device_register(&orion_ehci0); + platform_device_register(&orion5x_uart); + platform_device_register(&orion5x_ehci0); if (dev == MV88F5182_DEV_ID) - platform_device_register(&orion_ehci1); - platform_device_register(&orion_i2c); + platform_device_register(&orion5x_ehci1); + platform_device_register(&orion5x_i2c); } /* diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h new file mode 100644 index 00000000000..f4c4c9a72a7 --- /dev/null +++ b/arch/arm/mach-orion5x/common.h @@ -0,0 +1,72 @@ +#ifndef __ARCH_ORION5X_COMMON_H +#define __ARCH_ORION5X_COMMON_H + +/* + * Basic Orion init functions used early by machine-setup. + */ + +void orion5x_map_io(void); +void orion5x_init_irq(void); +void orion5x_init(void); +extern struct sys_timer orion5x_timer; + +/* + * Enumerations and functions for Orion windows mapping. Used by Orion core + * functions to map its interfaces and by the machine-setup to map its on- + * board devices. Details in /mach-orion/addr-map.c + */ +extern struct mbus_dram_target_info orion5x_mbus_dram_info; +void orion5x_setup_cpu_mbus_bridge(void); +void orion5x_setup_dev_boot_win(u32 base, u32 size); +void orion5x_setup_dev0_win(u32 base, u32 size); +void orion5x_setup_dev1_win(u32 base, u32 size); +void orion5x_setup_dev2_win(u32 base, u32 size); +void orion5x_setup_pcie_wa_win(u32 base, u32 size); +void orion5x_setup_eth_wins(void); + +/* + * Shared code used internally by other Orion core functions. + * (/mach-orion/pci.c) + */ + +struct pci_sys_data; +struct pci_bus; + +void orion5x_pcie_id(u32 *dev, u32 *rev); +int orion5x_pcie_local_bus_nr(void); +int orion5x_pci_local_bus_nr(void); +int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys); +struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); + +/* + * Valid GPIO pins according to MPP setup, used by machine-setup. + * (/mach-orion/gpio.c). + */ + +void orion5x_gpio_set_valid_pins(u32 pins); +void gpio_display(void); /* debug */ + +/* + * Pull in Orion Ethernet platform_data, used by machine-setup + */ + +struct mv643xx_eth_platform_data; + +void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data); + +/* + * Orion Sata platform_data, used by machine-setup + */ + +struct mv_sata_platform_data; + +void orion5x_sata_init(struct mv_sata_platform_data *sata_data); + +struct machine_desc; +struct meminfo; +struct tag; +extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *, + char **, struct meminfo *); + + +#endif diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c similarity index 90% rename from arch/arm/mach-orion/db88f5281-setup.c rename to arch/arm/mach-orion5x/db88f5281-setup.c index a0a9e4851b5..872aed37232 100644 --- a/arch/arm/mach-orion/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-orion/db88f5281-setup.c + * arch/arm/mach-orion5x/db88f5281-setup.c * * Marvell Orion-2 Development Board Setup * @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include "common.h" @@ -244,8 +244,8 @@ static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) /* * PCIE IRQ is connected internally (not GPIO) */ - if (dev->bus->number == orion_pcie_local_bus_nr()) - return IRQ_ORION_PCIE0_INT; + if (dev->bus->number == orion5x_pcie_local_bus_nr()) + return IRQ_ORION5X_PCIE0_INT; /* * PCI IRQs are connected via GPIOs @@ -265,8 +265,8 @@ static struct hw_pci db88f5281_pci __initdata = { .nr_controllers = 2, .preinit = db88f5281_pci_preinit, .swizzle = pci_std_swizzle, - .setup = orion_pci_sys_setup, - .scan = orion_pci_sys_scan_bus, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, .map_irq = db88f5281_pci_map_irq, }; @@ -312,16 +312,16 @@ static void __init db88f5281_init(void) /* * Basic Orion setup. Need to be called early. */ - orion_init(); + orion5x_init(); /* * Setup the CPU address decode windows for our on-board devices */ - orion_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, + orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, DB88F5281_NOR_BOOT_SIZE); - orion_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); - orion_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); - orion_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); + orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); + orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); + orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); /* * Setup Multiplexing Pins: @@ -337,25 +337,25 @@ static void __init db88f5281_init(void) * MPP18: UART1_CTS MPP19: UART1_RTS * MPP-DEV: DEV_D[16:31] */ - orion_write(MPP_0_7_CTRL, 0x00222203); - orion_write(MPP_8_15_CTRL, 0x44000000); - orion_write(MPP_16_19_CTRL, 0); - orion_write(MPP_DEV_CTRL, 0); + orion5x_write(MPP_0_7_CTRL, 0x00222203); + orion5x_write(MPP_8_15_CTRL, 0x44000000); + orion5x_write(MPP_16_19_CTRL, 0); + orion5x_write(MPP_DEV_CTRL, 0); - orion_gpio_set_valid_pins(0x00003fc3); + orion5x_gpio_set_valid_pins(0x00003fc3); platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs)); i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); - orion_eth_init(&db88f5281_eth_data); + orion5x_eth_init(&db88f5281_eth_data); } MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") /* Maintainer: Tzachi Perelstein */ - .phys_io = ORION_REGS_PHYS_BASE, - .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xfffc, + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xfffc, .boot_params = 0x00000100, .init_machine = db88f5281_init, - .map_io = orion_map_io, - .init_irq = orion_init_irq, - .timer = &orion_timer, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, MACHINE_END diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c similarity index 90% rename from arch/arm/mach-orion/dns323-setup.c rename to arch/arm/mach-orion5x/dns323-setup.c index 88991f76479..d67790ef236 100644 --- a/arch/arm/mach-orion/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-orion/dns323-setup.c + * arch/arm/mach-orion5x/dns323-setup.c * * Copyright (C) 2007 Herbert Valerio Riedel * @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include "common.h" #define DNS323_GPIO_LED_RIGHT_AMBER 1 @@ -44,8 +44,8 @@ static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { /* PCI-E */ - if (dev->bus->number == orion_pcie_local_bus_nr()) - return IRQ_ORION_PCIE0_INT; + if (dev->bus->number == orion5x_pcie_local_bus_nr()) + return IRQ_ORION5X_PCIE0_INT; pr_err("%s: requested mapping for unknown bus\n", __func__); @@ -55,8 +55,8 @@ static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci dns323_pci __initdata = { .nr_controllers = 1, .swizzle = pci_std_swizzle, - .setup = orion_pci_sys_setup, - .scan = orion_pci_sys_scan_bus, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, .map_irq = dns323_pci_map_irq, }; @@ -246,24 +246,25 @@ static void dns323_power_off(void) static void __init dns323_init(void) { /* Setup basic Orion functions. Need to be called early. */ - orion_init(); + orion5x_init(); /* setup flash mapping * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 */ - orion_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); + orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE * * Open a special address decode windows for the PCIE WA. */ - orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); + orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, + ORION5X_PCIE_WA_SIZE); /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ - orion_write(MPP_0_7_CTRL, 0); - orion_write(MPP_8_15_CTRL, 0); - orion_write(MPP_16_19_CTRL, 0); - orion_write(MPP_DEV_CTRL, 0); + orion5x_write(MPP_0_7_CTRL, 0); + orion5x_write(MPP_8_15_CTRL, 0); + orion5x_write(MPP_16_19_CTRL, 0); + orion5x_write(MPP_DEV_CTRL, 0); /* Define used GPIO pins @@ -286,7 +287,7 @@ static void __init dns323_init(void) | 14 | Out | //unknown// | 15 | Out | //unknown// */ - orion_gpio_set_valid_pins(0x07f6); + orion5x_gpio_set_valid_pins(0x07f6); /* register dns323 specific power-off method */ if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0) @@ -302,18 +303,18 @@ static void __init dns323_init(void) i2c_register_board_info(0, dns323_i2c_devices, ARRAY_SIZE(dns323_i2c_devices)); - orion_eth_init(&dns323_eth_data); + orion5x_eth_init(&dns323_eth_data); } /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ MACHINE_START(DNS323, "D-Link DNS-323") /* Maintainer: Herbert Valerio Riedel */ - .phys_io = ORION_REGS_PHYS_BASE, - .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, .boot_params = 0x00000100, .init_machine = dns323_init, - .map_io = orion_map_io, - .init_irq = orion_init_irq, - .timer = &orion_timer, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, .fixup = tag_fixup_mem32, MACHINE_END diff --git a/arch/arm/mach-orion/gpio.c b/arch/arm/mach-orion5x/gpio.c similarity index 71% rename from arch/arm/mach-orion/gpio.c rename to arch/arm/mach-orion5x/gpio.c index afc7be08b30..8108c316c42 100644 --- a/arch/arm/mach-orion/gpio.c +++ b/arch/arm/mach-orion5x/gpio.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-orion/gpio.c + * arch/arm/mach-orion5x/gpio.c * * GPIO functions for Marvell Orion System On Chip * @@ -17,14 +17,14 @@ #include #include #include -#include +#include #include "common.h" static DEFINE_SPINLOCK(gpio_lock); static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ -void __init orion_gpio_set_valid_pins(u32 pins) +void __init orion5x_gpio_set_valid_pins(u32 pins) { gpio_valid[0] = pins; } @@ -50,7 +50,7 @@ int gpio_direction_input(unsigned pin) if (!gpio_label[pin]) gpio_label[pin] = "?"; - orion_setbits(GPIO_IO_CONF, 1 << pin); + orion5x_setbits(GPIO_IO_CONF, 1 << pin); spin_unlock_irqrestore(&gpio_lock, flags); return 0; @@ -77,12 +77,12 @@ int gpio_direction_output(unsigned pin, int value) gpio_label[pin] = "?"; mask = 1 << pin; - orion_clrbits(GPIO_BLINK_EN, mask); + orion5x_clrbits(GPIO_BLINK_EN, mask); if (value) - orion_setbits(GPIO_OUT, mask); + orion5x_setbits(GPIO_OUT, mask); else - orion_clrbits(GPIO_OUT, mask); - orion_clrbits(GPIO_IO_CONF, mask); + orion5x_clrbits(GPIO_OUT, mask); + orion5x_clrbits(GPIO_IO_CONF, mask); spin_unlock_irqrestore(&gpio_lock, flags); return 0; @@ -93,10 +93,10 @@ int gpio_get_value(unsigned pin) { int val, mask = 1 << pin; - if (orion_read(GPIO_IO_CONF) & mask) - val = orion_read(GPIO_DATA_IN) ^ orion_read(GPIO_IN_POL); + if (orion5x_read(GPIO_IO_CONF) & mask) + val = orion5x_read(GPIO_DATA_IN) ^ orion5x_read(GPIO_IN_POL); else - val = orion_read(GPIO_OUT); + val = orion5x_read(GPIO_OUT); return val & mask; } @@ -109,32 +109,32 @@ void gpio_set_value(unsigned pin, int value) spin_lock_irqsave(&gpio_lock, flags); - orion_clrbits(GPIO_BLINK_EN, mask); + orion5x_clrbits(GPIO_BLINK_EN, mask); if (value) - orion_setbits(GPIO_OUT, mask); + orion5x_setbits(GPIO_OUT, mask); else - orion_clrbits(GPIO_OUT, mask); + orion5x_clrbits(GPIO_OUT, mask); spin_unlock_irqrestore(&gpio_lock, flags); } EXPORT_SYMBOL(gpio_set_value); -void orion_gpio_set_blink(unsigned pin, int blink) +void orion5x_gpio_set_blink(unsigned pin, int blink) { unsigned long flags; int mask = 1 << pin; spin_lock_irqsave(&gpio_lock, flags); - orion_clrbits(GPIO_OUT, mask); + orion5x_clrbits(GPIO_OUT, mask); if (blink) - orion_setbits(GPIO_BLINK_EN, mask); + orion5x_setbits(GPIO_BLINK_EN, mask); else - orion_clrbits(GPIO_BLINK_EN, mask); + orion5x_clrbits(GPIO_BLINK_EN, mask); spin_unlock_irqrestore(&gpio_lock, flags); } -EXPORT_SYMBOL(orion_gpio_set_blink); +EXPORT_SYMBOL(orion5x_gpio_set_blink); int gpio_request(unsigned pin, const char *label) { @@ -188,39 +188,39 @@ void gpio_display(void) printk("GPIO, free\n"); } else { printk("GPIO, used by %s, ", gpio_label[i]); - if (orion_read(GPIO_IO_CONF) & (1 << i)) { + if (orion5x_read(GPIO_IO_CONF) & (1 << i)) { printk("input, active %s, level %s, edge %s\n", - ((orion_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high", - ((orion_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", - ((orion_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); + ((orion5x_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high", + ((orion5x_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", + ((orion5x_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); } else { - printk("output, val=%d\n", (orion_read(GPIO_OUT) >> i) & 1); + printk("output, val=%d\n", (orion5x_read(GPIO_OUT) >> i) & 1); } } } printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n", - MPP_0_7_CTRL, orion_read(MPP_0_7_CTRL)); + MPP_0_7_CTRL, orion5x_read(MPP_0_7_CTRL)); printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n", - MPP_8_15_CTRL, orion_read(MPP_8_15_CTRL)); + MPP_8_15_CTRL, orion5x_read(MPP_8_15_CTRL)); printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n", - MPP_16_19_CTRL, orion_read(MPP_16_19_CTRL)); + MPP_16_19_CTRL, orion5x_read(MPP_16_19_CTRL)); printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n", - MPP_DEV_CTRL, orion_read(MPP_DEV_CTRL)); + MPP_DEV_CTRL, orion5x_read(MPP_DEV_CTRL)); printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n", - GPIO_OUT, orion_read(GPIO_OUT)); + GPIO_OUT, orion5x_read(GPIO_OUT)); printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n", - GPIO_IO_CONF, orion_read(GPIO_IO_CONF)); + GPIO_IO_CONF, orion5x_read(GPIO_IO_CONF)); printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n", - GPIO_BLINK_EN, orion_read(GPIO_BLINK_EN)); + GPIO_BLINK_EN, orion5x_read(GPIO_BLINK_EN)); printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n", - GPIO_IN_POL, orion_read(GPIO_IN_POL)); + GPIO_IN_POL, orion5x_read(GPIO_IN_POL)); printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n", - GPIO_DATA_IN, orion_read(GPIO_DATA_IN)); + GPIO_DATA_IN, orion5x_read(GPIO_DATA_IN)); printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n", - GPIO_LEVEL_MASK, orion_read(GPIO_LEVEL_MASK)); + GPIO_LEVEL_MASK, orion5x_read(GPIO_LEVEL_MASK)); printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n", - GPIO_EDGE_CAUSE, orion_read(GPIO_EDGE_CAUSE)); + GPIO_EDGE_CAUSE, orion5x_read(GPIO_EDGE_CAUSE)); printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n", - GPIO_EDGE_MASK, orion_read(GPIO_EDGE_MASK)); + GPIO_EDGE_MASK, orion5x_read(GPIO_EDGE_MASK)); } diff --git a/arch/arm/mach-orion/irq.c b/arch/arm/mach-orion5x/irq.c similarity index 62% rename from arch/arm/mach-orion/irq.c rename to arch/arm/mach-orion5x/irq.c index 7033cc1360e..dd21f38c5d3 100644 --- a/arch/arm/mach-orion/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-orion/irq.c + * arch/arm/mach-orion5x/irq.c * * Core IRQ functions for Marvell Orion System On Chip * @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include "common.h" @@ -44,46 +44,46 @@ * polarity LEVEL mask * ****************************************************************************/ -static void orion_gpio_irq_ack(u32 irq) +static void orion5x_gpio_irq_ack(u32 irq) { int pin = irq_to_gpio(irq); if (irq_desc[irq].status & IRQ_LEVEL) /* * Mask bit for level interrupt */ - orion_clrbits(GPIO_LEVEL_MASK, 1 << pin); + orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin); else /* * Clear casue bit for egde interrupt */ - orion_clrbits(GPIO_EDGE_CAUSE, 1 << pin); + orion5x_clrbits(GPIO_EDGE_CAUSE, 1 << pin); } -static void orion_gpio_irq_mask(u32 irq) +static void orion5x_gpio_irq_mask(u32 irq) { int pin = irq_to_gpio(irq); if (irq_desc[irq].status & IRQ_LEVEL) - orion_clrbits(GPIO_LEVEL_MASK, 1 << pin); + orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin); else - orion_clrbits(GPIO_EDGE_MASK, 1 << pin); + orion5x_clrbits(GPIO_EDGE_MASK, 1 << pin); } -static void orion_gpio_irq_unmask(u32 irq) +static void orion5x_gpio_irq_unmask(u32 irq) { int pin = irq_to_gpio(irq); if (irq_desc[irq].status & IRQ_LEVEL) - orion_setbits(GPIO_LEVEL_MASK, 1 << pin); + orion5x_setbits(GPIO_LEVEL_MASK, 1 << pin); else - orion_setbits(GPIO_EDGE_MASK, 1 << pin); + orion5x_setbits(GPIO_EDGE_MASK, 1 << pin); } -static int orion_gpio_set_irq_type(u32 irq, u32 type) +static int orion5x_gpio_set_irq_type(u32 irq, u32 type) { int pin = irq_to_gpio(irq); struct irq_desc *desc; - if ((orion_read(GPIO_IO_CONF) & (1 << pin)) == 0) { - printk(KERN_ERR "orion_gpio_set_irq_type failed " + if ((orion5x_read(GPIO_IO_CONF) & (1 << pin)) == 0) { + printk(KERN_ERR "orion5x_gpio_set_irq_type failed " "(irq %d, pin %d).\n", irq, pin); return -EINVAL; } @@ -94,22 +94,22 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type) case IRQT_HIGH: desc->handle_irq = handle_level_irq; desc->status |= IRQ_LEVEL; - orion_clrbits(GPIO_IN_POL, (1 << pin)); + orion5x_clrbits(GPIO_IN_POL, (1 << pin)); break; case IRQT_LOW: desc->handle_irq = handle_level_irq; desc->status |= IRQ_LEVEL; - orion_setbits(GPIO_IN_POL, (1 << pin)); + orion5x_setbits(GPIO_IN_POL, (1 << pin)); break; case IRQT_RISING: desc->handle_irq = handle_edge_irq; desc->status &= ~IRQ_LEVEL; - orion_clrbits(GPIO_IN_POL, (1 << pin)); + orion5x_clrbits(GPIO_IN_POL, (1 << pin)); break; case IRQT_FALLING: desc->handle_irq = handle_edge_irq; desc->status &= ~IRQ_LEVEL; - orion_setbits(GPIO_IN_POL, (1 << pin)); + orion5x_setbits(GPIO_IN_POL, (1 << pin)); break; case IRQT_BOTHEDGE: desc->handle_irq = handle_edge_irq; @@ -117,11 +117,11 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type) /* * set initial polarity based on current input level */ - if ((orion_read(GPIO_IN_POL) ^ orion_read(GPIO_DATA_IN)) + if ((orion5x_read(GPIO_IN_POL) ^ orion5x_read(GPIO_DATA_IN)) & (1 << pin)) - orion_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ + orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ else - orion_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */ + orion5x_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */ break; default: @@ -135,22 +135,22 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type) return 0; } -static struct irq_chip orion_gpio_irq_chip = { +static struct irq_chip orion5x_gpio_irq_chip = { .name = "Orion-IRQ-GPIO", - .ack = orion_gpio_irq_ack, - .mask = orion_gpio_irq_mask, - .unmask = orion_gpio_irq_unmask, - .set_type = orion_gpio_set_irq_type, + .ack = orion5x_gpio_irq_ack, + .mask = orion5x_gpio_irq_mask, + .unmask = orion5x_gpio_irq_unmask, + .set_type = orion5x_gpio_set_irq_type, }; -static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { u32 cause, offs, pin; - BUG_ON(irq < IRQ_ORION_GPIO_0_7 || irq > IRQ_ORION_GPIO_24_31); - offs = (irq - IRQ_ORION_GPIO_0_7) * 8; - cause = (orion_read(GPIO_DATA_IN) & orion_read(GPIO_LEVEL_MASK)) | - (orion_read(GPIO_EDGE_CAUSE) & orion_read(GPIO_EDGE_MASK)); + BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31); + offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8; + cause = (orion5x_read(GPIO_DATA_IN) & orion5x_read(GPIO_LEVEL_MASK)) | + (orion5x_read(GPIO_EDGE_CAUSE) & orion5x_read(GPIO_EDGE_MASK)); for (pin = offs; pin < offs + 8; pin++) { if (cause & (1 << pin)) { @@ -158,16 +158,16 @@ static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) desc = irq_desc + irq; if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { /* Swap polarity (race with GPIO line) */ - u32 polarity = orion_read(GPIO_IN_POL); + u32 polarity = orion5x_read(GPIO_IN_POL); polarity ^= 1 << pin; - orion_write(GPIO_IN_POL, polarity); + orion5x_write(GPIO_IN_POL, polarity); } desc_handle_irq(irq, desc); } } } -static void __init orion_init_gpio_irq(void) +static void __init orion5x_init_gpio_irq(void) { int i; struct irq_desc *desc; @@ -175,37 +175,37 @@ static void __init orion_init_gpio_irq(void) /* * Mask and clear GPIO IRQ interrupts */ - orion_write(GPIO_LEVEL_MASK, 0x0); - orion_write(GPIO_EDGE_MASK, 0x0); - orion_write(GPIO_EDGE_CAUSE, 0x0); + orion5x_write(GPIO_LEVEL_MASK, 0x0); + orion5x_write(GPIO_EDGE_MASK, 0x0); + orion5x_write(GPIO_EDGE_CAUSE, 0x0); /* * Register chained level handlers for GPIO IRQs by default. * User can use set_type() if he wants to use edge types handlers. */ - for (i = IRQ_ORION_GPIO_START; i < NR_IRQS; i++) { - set_irq_chip(i, &orion_gpio_irq_chip); + for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) { + set_irq_chip(i, &orion5x_gpio_irq_chip); set_irq_handler(i, handle_level_irq); desc = irq_desc + i; desc->status |= IRQ_LEVEL; set_irq_flags(i, IRQF_VALID); } - set_irq_chained_handler(IRQ_ORION_GPIO_0_7, orion_gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION_GPIO_8_15, orion_gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION_GPIO_16_23, orion_gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION_GPIO_24_31, orion_gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, orion5x_gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, orion5x_gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, orion5x_gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, orion5x_gpio_irq_handler); } /***************************************************************************** * Orion Main IRQ ****************************************************************************/ -static void __init orion_init_main_irq(void) +static void __init orion5x_init_main_irq(void) { orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); } -void __init orion_init_irq(void) +void __init orion5x_init_irq(void) { - orion_init_main_irq(); - orion_init_gpio_irq(); + orion5x_init_main_irq(); + orion5x_init_gpio_irq(); } diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c similarity index 86% rename from arch/arm/mach-orion/kurobox_pro-setup.c rename to arch/arm/mach-orion5x/kurobox_pro-setup.c index be417e7f423..8ad4390b4b7 100644 --- a/arch/arm/mach-orion/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-orion/kurobox_pro-setup.c + * arch/arm/mach-orion5x/kurobox_pro-setup.c * * Maintainer: Ronen Shitrit * @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include "common.h" @@ -123,8 +123,8 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) /* * PCI isn't used on the Kuro */ - if (dev->bus->number == orion_pcie_local_bus_nr()) - return IRQ_ORION_PCIE0_INT; + if (dev->bus->number == orion5x_pcie_local_bus_nr()) + return IRQ_ORION5X_PCIE0_INT; else printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n"); @@ -134,8 +134,8 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci kurobox_pro_pci __initdata = { .nr_controllers = 1, .swizzle = pci_std_swizzle, - .setup = orion_pci_sys_setup, - .scan = orion_pci_sys_scan_bus, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, .map_irq = kurobox_pro_pci_map_irq, }; @@ -188,19 +188,20 @@ static void __init kurobox_pro_init(void) /* * Setup basic Orion functions. Need to be called early. */ - orion_init(); + orion5x_init(); /* * Setup the CPU address decode windows for our devices */ - orion_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, + orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, KUROBOX_PRO_NOR_BOOT_SIZE); - orion_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE); + orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE); /* * Open a special address decode windows for the PCIE WA. */ - orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); + orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, + ORION5X_PCIE_WA_SIZE); /* * Setup Multiplexing Pins -- @@ -217,26 +218,26 @@ static void __init kurobox_pro_init(void) * MPP[15] SATA 1 active indication * MPP[16-19] Not used */ - orion_write(MPP_0_7_CTRL, 0x44220003); - orion_write(MPP_8_15_CTRL, 0x55550000); - orion_write(MPP_16_19_CTRL, 0x0); + orion5x_write(MPP_0_7_CTRL, 0x44220003); + orion5x_write(MPP_8_15_CTRL, 0x55550000); + orion5x_write(MPP_16_19_CTRL, 0x0); - orion_gpio_set_valid_pins(0x0000000c); + orion5x_gpio_set_valid_pins(0x0000000c); platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices)); i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1); - orion_eth_init(&kurobox_pro_eth_data); - orion_sata_init(&kurobox_pro_sata_data); + orion5x_eth_init(&kurobox_pro_eth_data); + orion5x_sata_init(&kurobox_pro_sata_data); } MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") /* Maintainer: Ronen Shitrit */ - .phys_io = ORION_REGS_PHYS_BASE, - .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, .boot_params = 0x00000100, .init_machine = kurobox_pro_init, - .map_io = orion_map_io, - .init_irq = orion_init_irq, - .timer = &orion_timer, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, .fixup = tag_fixup_mem32, MACHINE_END diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion5x/pci.c similarity index 71% rename from arch/arm/mach-orion/pci.c rename to arch/arm/mach-orion5x/pci.c index 59684cc329b..27b4afc8f48 100644 --- a/arch/arm/mach-orion/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-orion/pci.c + * arch/arm/mach-orion5x/pci.c * * PCI and PCIe functions for Marvell Orion System On Chip * @@ -33,15 +33,15 @@ /***************************************************************************** * PCIe controller ****************************************************************************/ -#define PCIE_BASE ((void __iomem *)ORION_PCIE_VIRT_BASE) +#define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) -void __init orion_pcie_id(u32 *dev, u32 *rev) +void __init orion5x_pcie_id(u32 *dev, u32 *rev) { *dev = orion_pcie_dev_id(PCIE_BASE); *rev = orion_pcie_rev(PCIE_BASE); } -int orion_pcie_local_bus_nr(void) +int orion5x_pcie_local_bus_nr(void) { return orion_pcie_get_local_bus_nr(PCIE_BASE); } @@ -71,7 +71,7 @@ static int pcie_valid_config(int bus, int dev) * and then reading the PCIE_CONF_DATA register. Need to make sure these * transactions are atomic. */ -static DEFINE_SPINLOCK(orion_pcie_lock); +static DEFINE_SPINLOCK(orion5x_pcie_lock); static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) @@ -84,9 +84,9 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, return PCIBIOS_DEVICE_NOT_FOUND; } - spin_lock_irqsave(&orion_pcie_lock, flags); + spin_lock_irqsave(&orion5x_pcie_lock, flags); ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); - spin_unlock_irqrestore(&orion_pcie_lock, flags); + spin_unlock_irqrestore(&orion5x_pcie_lock, flags); return ret; } @@ -111,7 +111,7 @@ static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, return PCIBIOS_DEVICE_NOT_FOUND; } - ret = orion_pcie_rd_conf_wa((void __iomem *)ORION_PCIE_WA_VIRT_BASE, + ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, bus, devfn, where, size, val); return ret; @@ -126,9 +126,9 @@ static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) return PCIBIOS_DEVICE_NOT_FOUND; - spin_lock_irqsave(&orion_pcie_lock, flags); + spin_lock_irqsave(&orion5x_pcie_lock, flags); ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); - spin_unlock_irqrestore(&orion_pcie_lock, flags); + spin_unlock_irqrestore(&orion5x_pcie_lock, flags); return ret; } @@ -147,7 +147,7 @@ static int __init pcie_setup(struct pci_sys_data *sys) /* * Generic PCIe unit setup. */ - orion_pcie_setup(PCIE_BASE, &orion_mbus_dram_info); + orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); /* * Check whether to apply Orion-1/Orion-NAS PCIe config @@ -172,8 +172,8 @@ static int __init pcie_setup(struct pci_sys_data *sys) */ res[0].name = "PCIe I/O Space"; res[0].flags = IORESOURCE_IO; - res[0].start = ORION_PCIE_IO_BUS_BASE; - res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1; + res[0].start = ORION5X_PCIE_IO_BUS_BASE; + res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; if (request_resource(&ioport_resource, &res[0])) panic("Request PCIe IO resource failed\n"); sys->resource[0] = &res[0]; @@ -183,8 +183,8 @@ static int __init pcie_setup(struct pci_sys_data *sys) */ res[1].name = "PCIe Memory Space"; res[1].flags = IORESOURCE_MEM; - res[1].start = ORION_PCIE_MEM_PHYS_BASE; - res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1; + res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; + res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; if (request_resource(&iomem_resource, &res[1])) panic("Request PCIe Memory resource failed\n"); sys->resource[1] = &res[1]; @@ -198,11 +198,11 @@ static int __init pcie_setup(struct pci_sys_data *sys) /***************************************************************************** * PCI controller ****************************************************************************/ -#define PCI_MODE ORION_PCI_REG(0xd00) -#define PCI_CMD ORION_PCI_REG(0xc00) -#define PCI_P2P_CONF ORION_PCI_REG(0x1d14) -#define PCI_CONF_ADDR ORION_PCI_REG(0xc78) -#define PCI_CONF_DATA ORION_PCI_REG(0xc7c) +#define PCI_MODE ORION5X_PCI_REG(0xd00) +#define PCI_CMD ORION5X_PCI_REG(0xc00) +#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) +#define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) +#define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) /* * PCI_MODE bits @@ -244,16 +244,16 @@ static int __init pcie_setup(struct pci_sys_data *sys) /* * PCI Address Decode Windows registers */ -#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \ - ((n) == 1) ? ORION_PCI_REG(0xd08) : \ - ((n) == 2) ? ORION_PCI_REG(0xc0c) : \ - ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0) -#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \ - ((n) == 1) ? ORION_PCI_REG(0xd48) : \ - ((n) == 2) ? ORION_PCI_REG(0xc4c) : \ - ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0) -#define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c) -#define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c) +#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ + ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ + ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ + ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) +#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION5X_PCI_REG(0xc48) : \ + ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ + ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ + ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) +#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) +#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) /* * PCI configuration helpers for BAR settings @@ -267,45 +267,45 @@ static int __init pcie_setup(struct pci_sys_data *sys) * and then reading the PCI_CONF_DATA register. Need to make sure these * transactions are atomic. */ -static DEFINE_SPINLOCK(orion_pci_lock); +static DEFINE_SPINLOCK(orion5x_pci_lock); -int orion_pci_local_bus_nr(void) +int orion5x_pci_local_bus_nr(void) { - u32 conf = orion_read(PCI_P2P_CONF); + u32 conf = orion5x_read(PCI_P2P_CONF); return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); } -static int orion_pci_hw_rd_conf(int bus, int dev, u32 func, +static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, u32 where, u32 size, u32 *val) { unsigned long flags; - spin_lock_irqsave(&orion_pci_lock, flags); + spin_lock_irqsave(&orion5x_pci_lock, flags); - orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | + orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); - *val = orion_read(PCI_CONF_DATA); + *val = orion5x_read(PCI_CONF_DATA); if (size == 1) *val = (*val >> (8*(where & 0x3))) & 0xff; else if (size == 2) *val = (*val >> (8*(where & 0x3))) & 0xffff; - spin_unlock_irqrestore(&orion_pci_lock, flags); + spin_unlock_irqrestore(&orion5x_pci_lock, flags); return PCIBIOS_SUCCESSFUL; } -static int orion_pci_hw_wr_conf(int bus, int dev, u32 func, +static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, u32 where, u32 size, u32 val) { unsigned long flags; int ret = PCIBIOS_SUCCESSFUL; - spin_lock_irqsave(&orion_pci_lock, flags); + spin_lock_irqsave(&orion5x_pci_lock, flags); - orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | + orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); @@ -319,82 +319,82 @@ static int orion_pci_hw_wr_conf(int bus, int dev, u32 func, ret = PCIBIOS_BAD_REGISTER_NUMBER; } - spin_unlock_irqrestore(&orion_pci_lock, flags); + spin_unlock_irqrestore(&orion5x_pci_lock, flags); return ret; } -static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn, +static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { /* * Don't go out for local device */ - if (bus->number == orion_pci_local_bus_nr() && + if (bus->number == orion5x_pci_local_bus_nr() && PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) { *val = 0xffffffff; return PCIBIOS_DEVICE_NOT_FOUND; } - return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), + return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val); } -static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn, +static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - if (bus->number == orion_pci_local_bus_nr() && + if (bus->number == orion5x_pci_local_bus_nr() && PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) return PCIBIOS_DEVICE_NOT_FOUND; - return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), + return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val); } static struct pci_ops pci_ops = { - .read = orion_pci_rd_conf, - .write = orion_pci_wr_conf, + .read = orion5x_pci_rd_conf, + .write = orion5x_pci_wr_conf, }; -static void __init orion_pci_set_bus_nr(int nr) +static void __init orion5x_pci_set_bus_nr(int nr) { - u32 p2p = orion_read(PCI_P2P_CONF); + u32 p2p = orion5x_read(PCI_P2P_CONF); - if (orion_read(PCI_MODE) & PCI_MODE_PCIX) { + if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) { /* * PCI-X mode */ u32 pcix_status, bus, dev; bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; - orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); + orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); pcix_status &= ~PCIX_STAT_BUS_MASK; pcix_status |= (nr << PCIX_STAT_BUS_OFFS); - orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); + orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); } else { /* * PCI Conventional mode */ p2p &= ~PCI_P2P_BUS_MASK; p2p |= (nr << PCI_P2P_BUS_OFFS); - orion_write(PCI_P2P_CONF, p2p); + orion5x_write(PCI_P2P_CONF, p2p); } } -static void __init orion_pci_master_slave_enable(void) +static void __init orion5x_pci_master_slave_enable(void) { int bus_nr, func, reg; u32 val; - bus_nr = orion_pci_local_bus_nr(); + bus_nr = orion5x_pci_local_bus_nr(); func = PCI_CONF_FUNC_STAT_CMD; reg = PCI_CONF_REG_STAT_CMD; - orion_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); + orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - orion_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); + orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); } -static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) +static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) { u32 win_enable; int bus; @@ -404,12 +404,12 @@ static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) * First, disable windows. */ win_enable = 0xffffffff; - orion_write(PCI_BAR_ENABLE, win_enable); + orion5x_write(PCI_BAR_ENABLE, win_enable); /* * Setup windows for DDR banks. */ - bus = orion_pci_local_bus_nr(); + bus = orion5x_pci_local_bus_nr(); for (i = 0; i < dram->num_cs; i++) { struct mbus_dram_window *cs = dram->cs + i; @@ -421,18 +421,18 @@ static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) * Write DRAM bank base address register. */ reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); - orion_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); + orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); val = (cs->base & 0xfffff000) | (val & 0xfff); - orion_pci_hw_wr_conf(bus, 0, func, reg, 4, val); + orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); /* * Write DRAM bank size register. */ reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); - orion_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); - orion_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), + orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); + orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), (cs->size - 1) & 0xfffff000); - orion_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), + orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), cs->base & 0xfffff000); /* @@ -444,12 +444,12 @@ static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) /* * Re-enable decode windows. */ - orion_write(PCI_BAR_ENABLE, win_enable); + orion5x_write(PCI_BAR_ENABLE, win_enable); /* * Disable automatic update of address remaping when writing to BARs. */ - orion_setbits(PCI_ADDR_DECODE_CTRL, 1); + orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); } static int __init pci_setup(struct pci_sys_data *sys) @@ -459,17 +459,17 @@ static int __init pci_setup(struct pci_sys_data *sys) /* * Point PCI unit MBUS decode windows to DRAM space. */ - orion_setup_pci_wins(&orion_mbus_dram_info); + orion5x_setup_pci_wins(&orion5x_mbus_dram_info); /* * Master + Slave enable */ - orion_pci_master_slave_enable(); + orion5x_pci_master_slave_enable(); /* * Force ordering */ - orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); + orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); /* * Request resources @@ -483,8 +483,8 @@ static int __init pci_setup(struct pci_sys_data *sys) */ res[0].name = "PCI I/O Space"; res[0].flags = IORESOURCE_IO; - res[0].start = ORION_PCI_IO_BUS_BASE; - res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1; + res[0].start = ORION5X_PCI_IO_BUS_BASE; + res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; if (request_resource(&ioport_resource, &res[0])) panic("Request PCI IO resource failed\n"); sys->resource[0] = &res[0]; @@ -494,8 +494,8 @@ static int __init pci_setup(struct pci_sys_data *sys) */ res[1].name = "PCI Memory Space"; res[1].flags = IORESOURCE_MEM; - res[1].start = ORION_PCI_MEM_PHYS_BASE; - res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1; + res[1].start = ORION5X_PCI_MEM_PHYS_BASE; + res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; if (request_resource(&iomem_resource, &res[1])) panic("Request PCI Memory resource failed\n"); sys->resource[1] = &res[1]; @@ -527,7 +527,7 @@ static void __devinit rc_pci_fixup(struct pci_dev *dev) } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); -int __init orion_pci_sys_setup(int nr, struct pci_sys_data *sys) +int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) { int ret = 0; @@ -535,14 +535,14 @@ int __init orion_pci_sys_setup(int nr, struct pci_sys_data *sys) orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); ret = pcie_setup(sys); } else if (nr == 1) { - orion_pci_set_bus_nr(sys->busnr); + orion5x_pci_set_bus_nr(sys->busnr); ret = pci_setup(sys); } return ret; } -struct pci_bus __init *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) +struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) { struct pci_bus *bus; diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c similarity index 89% rename from arch/arm/mach-orion/rd88f5182-setup.c rename to arch/arm/mach-orion5x/rd88f5182-setup.c index f3e38ecda1c..37e8b2dc3ed 100644 --- a/arch/arm/mach-orion/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-orion/rd88f5182-setup.c + * arch/arm/mach-orion5x/rd88f5182-setup.c * * Marvell Orion-NAS Reference Design Setup * @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include "common.h" /***************************************************************************** @@ -175,8 +175,8 @@ static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) /* * PCI-E isn't used on the RD2 */ - if (dev->bus->number == orion_pcie_local_bus_nr()) - return IRQ_ORION_PCIE0_INT; + if (dev->bus->number == orion5x_pcie_local_bus_nr()) + return IRQ_ORION5X_PCIE0_INT; /* * PCI IRQs are connected via GPIOs @@ -196,8 +196,8 @@ static struct hw_pci rd88f5182_pci __initdata = { .nr_controllers = 2, .preinit = rd88f5182_pci_preinit, .swizzle = pci_std_swizzle, - .setup = orion_pci_sys_setup, - .scan = orion_pci_sys_scan_bus, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, .map_irq = rd88f5182_pci_map_irq, }; @@ -249,19 +249,20 @@ static void __init rd88f5182_init(void) /* * Setup basic Orion functions. Need to be called early. */ - orion_init(); + orion5x_init(); /* * Setup the CPU address decode windows for our devices */ - orion_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, + orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, RD88F5182_NOR_BOOT_SIZE); - orion_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); + orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); /* * Open a special address decode windows for the PCIE WA. */ - orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); + orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, + ORION5X_PCIE_WA_SIZE); /* * Setup Multiplexing Pins -- @@ -287,25 +288,25 @@ static void __init rd88f5182_init(void) * MPP[25] USB 0 over current enable */ - orion_write(MPP_0_7_CTRL, 0x00000003); - orion_write(MPP_8_15_CTRL, 0x55550000); - orion_write(MPP_16_19_CTRL, 0x5555); + orion5x_write(MPP_0_7_CTRL, 0x00000003); + orion5x_write(MPP_8_15_CTRL, 0x55550000); + orion5x_write(MPP_16_19_CTRL, 0x5555); - orion_gpio_set_valid_pins(0x000000fb); + orion5x_gpio_set_valid_pins(0x000000fb); platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices)); i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); - orion_eth_init(&rd88f5182_eth_data); - orion_sata_init(&rd88f5182_sata_data); + orion5x_eth_init(&rd88f5182_eth_data); + orion5x_sata_init(&rd88f5182_sata_data); } MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") /* Maintainer: Ronen Shitrit */ - .phys_io = ORION_REGS_PHYS_BASE, - .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, .boot_params = 0x00000100, .init_machine = rd88f5182_init, - .map_io = orion_map_io, - .init_irq = orion_init_irq, - .timer = &orion_timer, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, MACHINE_END diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c similarity index 88% rename from arch/arm/mach-orion/ts209-setup.c rename to arch/arm/mach-orion5x/ts209-setup.c index 8eca070006f..71b0cffa2fe 100644 --- a/arch/arm/mach-orion/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include "common.h" #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000 @@ -144,8 +144,8 @@ static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) /* * PCIE IRQ is connected internally (not GPIO) */ - if (dev->bus->number == orion_pcie_local_bus_nr()) - return IRQ_ORION_PCIE0_INT; + if (dev->bus->number == orion5x_pcie_local_bus_nr()) + return IRQ_ORION5X_PCIE0_INT; /* * PCI IRQs are connected via GPIOs @@ -164,8 +164,8 @@ static struct hw_pci qnap_ts209_pci __initdata = { .nr_controllers = 2, .preinit = qnap_ts209_pci_preinit, .swizzle = pci_std_swizzle, - .setup = orion_pci_sys_setup, - .scan = orion_pci_sys_scan_bus, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, .map_irq = qnap_ts209_pci_map_irq, }; @@ -261,21 +261,21 @@ static struct platform_device *qnap_ts209_devices[] __initdata = { static void qnap_ts209_power_off(void) { /* 19200 baud divisor */ - const unsigned divisor = ((ORION_TCLK + (8 * 19200)) / (16 * 19200)); + const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200)); pr_info("%s: triggering power-off...\n", __func__); /* hijack uart1 and reset into sane state (19200,8n1) */ - orion_write(UART1_REG(LCR), 0x83); - orion_write(UART1_REG(DLL), divisor & 0xff); - orion_write(UART1_REG(DLM), (divisor >> 8) & 0xff); - orion_write(UART1_REG(LCR), 0x03); - orion_write(UART1_REG(IER), 0x00); - orion_write(UART1_REG(FCR), 0x00); - orion_write(UART1_REG(MCR), 0x00); + orion5x_write(UART1_REG(LCR), 0x83); + orion5x_write(UART1_REG(DLL), divisor & 0xff); + orion5x_write(UART1_REG(DLM), (divisor >> 8) & 0xff); + orion5x_write(UART1_REG(LCR), 0x03); + orion5x_write(UART1_REG(IER), 0x00); + orion5x_write(UART1_REG(FCR), 0x00); + orion5x_write(UART1_REG(MCR), 0x00); /* send the power-off command 'A' to PIC */ - orion_write(UART1_REG(TX), 'A'); + orion5x_write(UART1_REG(TX), 'A'); } static void __init qnap_ts209_init(void) @@ -283,18 +283,19 @@ static void __init qnap_ts209_init(void) /* * Setup basic Orion functions. Need to be called early. */ - orion_init(); + orion5x_init(); /* * Setup flash mapping */ - orion_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, + orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, QNAP_TS209_NOR_BOOT_SIZE); /* * Open a special address decode windows for the PCIE WA. */ - orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); + orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, + ORION5X_PCIE_WA_SIZE); /* * Setup Multiplexing Pins -- @@ -319,10 +320,10 @@ static void __init qnap_ts209_init(void) * MPP[22] USB 0 over current * MPP[23-25] Reserved */ - orion_write(MPP_0_7_CTRL, 0x3); - orion_write(MPP_8_15_CTRL, 0x55550000); - orion_write(MPP_16_19_CTRL, 0x5500); - orion_gpio_set_valid_pins(0x3cc0fff); + orion5x_write(MPP_0_7_CTRL, 0x3); + orion5x_write(MPP_8_15_CTRL, 0x55550000); + orion5x_write(MPP_16_19_CTRL, 0x5500); + orion5x_gpio_set_valid_pins(0x3cc0fff); /* register ts209 specific power-off method */ pm_power_off = qnap_ts209_power_off; @@ -341,18 +342,18 @@ static void __init qnap_ts209_init(void) pr_warning("qnap_ts209_init: failed to get RTC IRQ\n"); i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); - orion_eth_init(&qnap_ts209_eth_data); - orion_sata_init(&qnap_ts209_sata_data); + orion5x_eth_init(&qnap_ts209_eth_data); + orion5x_sata_init(&qnap_ts209_sata_data); } MACHINE_START(TS209, "QNAP TS-109/TS-209") /* Maintainer: Byron Bradley */ - .phys_io = ORION_REGS_PHYS_BASE, - .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, .boot_params = 0x00000100, .init_machine = qnap_ts209_init, - .map_io = orion_map_io, - .init_irq = orion_init_irq, - .timer = &orion_timer, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, .fixup = tag_fixup_mem32, MACHINE_END diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 76348f060f2..64d09244df4 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -345,7 +345,7 @@ config CPU_XSC3 # Feroceon config CPU_FEROCEON bool - depends on ARCH_ORION + depends on ARCH_ORION5X default y select CPU_32v5 select CPU_ABRT_EV5T diff --git a/include/asm-arm/arch-orion/irqs.h b/include/asm-arm/arch-orion/irqs.h deleted file mode 100644 index 70a2420456a..00000000000 --- a/include/asm-arm/arch-orion/irqs.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * include/asm-arm/arch-orion/irqs.h - * - * IRQ definitions for Orion SoC - * - * Maintainer: Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -#include "orion.h" /* need GPIO_MAX */ - -/* - * Orion Main Interrupt Controller - */ -#define IRQ_ORION_BRIDGE 0 -#define IRQ_ORION_DOORBELL_H2C 1 -#define IRQ_ORION_DOORBELL_C2H 2 -#define IRQ_ORION_UART0 3 -#define IRQ_ORION_UART1 4 -#define IRQ_ORION_I2C 5 -#define IRQ_ORION_GPIO_0_7 6 -#define IRQ_ORION_GPIO_8_15 7 -#define IRQ_ORION_GPIO_16_23 8 -#define IRQ_ORION_GPIO_24_31 9 -#define IRQ_ORION_PCIE0_ERR 10 -#define IRQ_ORION_PCIE0_INT 11 -#define IRQ_ORION_USB1_CTRL 12 -#define IRQ_ORION_DEV_BUS_ERR 14 -#define IRQ_ORION_PCI_ERR 15 -#define IRQ_ORION_USB_BR_ERR 16 -#define IRQ_ORION_USB0_CTRL 17 -#define IRQ_ORION_ETH_RX 18 -#define IRQ_ORION_ETH_TX 19 -#define IRQ_ORION_ETH_MISC 20 -#define IRQ_ORION_ETH_SUM 21 -#define IRQ_ORION_ETH_ERR 22 -#define IRQ_ORION_IDMA_ERR 23 -#define IRQ_ORION_IDMA_0 24 -#define IRQ_ORION_IDMA_1 25 -#define IRQ_ORION_IDMA_2 26 -#define IRQ_ORION_IDMA_3 27 -#define IRQ_ORION_CESA 28 -#define IRQ_ORION_SATA 29 -#define IRQ_ORION_XOR0 30 -#define IRQ_ORION_XOR1 31 - -/* - * Orion General Purpose Pins - */ -#define IRQ_ORION_GPIO_START 32 -#define NR_GPIO_IRQS GPIO_MAX - -#define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS) - - -#endif diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h deleted file mode 100644 index 01f1299472d..00000000000 --- a/include/asm-arm/arch-orion/orion.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * include/asm-arm/arch-orion/orion.h - * - * Generic definitions of Orion SoC flavors: - * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2. - * - * Maintainer: Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_ORION_H -#define __ASM_ARCH_ORION_H - -/***************************************************************************** - * Orion Address Maps - * - * phys - * e0000000 PCIe MEM space - * e8000000 PCI MEM space - * f0000000 PCIe WA space (Orion-1/Orion-NAS only) - * f1000000 on-chip peripheral registers - * f2000000 PCIe I/O space - * f2100000 PCI I/O space - * f4000000 device bus mappings (boot) - * fa000000 device bus mappings (cs0) - * fa800000 device bus mappings (cs2) - * fc000000 device bus mappings (cs0/cs1) - * - * virt phys size - * fdd00000 f1000000 1M on-chip peripheral registers - * fde00000 f2000000 1M PCIe I/O space - * fdf00000 f2100000 1M PCI I/O space - * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) - ****************************************************************************/ -#define ORION_REGS_PHYS_BASE 0xf1000000 -#define ORION_REGS_VIRT_BASE 0xfdd00000 -#define ORION_REGS_SIZE SZ_1M - -#define ORION_PCIE_IO_PHYS_BASE 0xf2000000 -#define ORION_PCIE_IO_VIRT_BASE 0xfde00000 -#define ORION_PCIE_IO_BUS_BASE 0x00000000 -#define ORION_PCIE_IO_SIZE SZ_1M - -#define ORION_PCI_IO_PHYS_BASE 0xf2100000 -#define ORION_PCI_IO_VIRT_BASE 0xfdf00000 -#define ORION_PCI_IO_BUS_BASE 0x00100000 -#define ORION_PCI_IO_SIZE SZ_1M - -/* Relevant only for Orion-1/Orion-NAS */ -#define ORION_PCIE_WA_PHYS_BASE 0xf0000000 -#define ORION_PCIE_WA_VIRT_BASE 0xfe000000 -#define ORION_PCIE_WA_SIZE SZ_16M - -#define ORION_PCIE_MEM_PHYS_BASE 0xe0000000 -#define ORION_PCIE_MEM_SIZE SZ_128M - -#define ORION_PCI_MEM_PHYS_BASE 0xe8000000 -#define ORION_PCI_MEM_SIZE SZ_128M - -/******************************************************************************* - * Supported Devices & Revisions - ******************************************************************************/ -/* Orion-1 (88F5181) */ -#define MV88F5181_DEV_ID 0x5181 -#define MV88F5181_REV_B1 3 -/* Orion-NAS (88F5182) */ -#define MV88F5182_DEV_ID 0x5182 -#define MV88F5182_REV_A2 2 -/* Orion-2 (88F5281) */ -#define MV88F5281_DEV_ID 0x5281 -#define MV88F5281_REV_D1 5 -#define MV88F5281_REV_D2 6 - -/******************************************************************************* - * Orion Registers Map - ******************************************************************************/ -#define ORION_DDR_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x00000) -#define ORION_DDR_REG(x) (ORION_DDR_VIRT_BASE | (x)) - -#define ORION_DEV_BUS_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x10000) -#define ORION_DEV_BUS_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x10000) -#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_VIRT_BASE | (x)) -#define I2C_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x1000) -#define UART0_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2000) -#define UART0_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2000) -#define UART1_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2100) -#define UART1_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2100) - -#define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000) -#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x)) -#define TIMER_VIRT_BASE (ORION_BRIDGE_VIRT_BASE | 0x300) - -#define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000) -#define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x)) - -#define ORION_PCIE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x40000) -#define ORION_PCIE_REG(x) (ORION_PCIE_VIRT_BASE | (x)) - -#define ORION_USB0_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x50000) -#define ORION_USB0_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x50000) -#define ORION_USB0_REG(x) (ORION_USB0_VIRT_BASE | (x)) - -#define ORION_ETH_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x70000) -#define ORION_ETH_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x70000) -#define ORION_ETH_REG(x) (ORION_ETH_VIRT_BASE | (x)) - -#define ORION_SATA_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x80000) -#define ORION_SATA_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x80000) -#define ORION_SATA_REG(x) (ORION_SATA_VIRT_BASE | (x)) - -#define ORION_USB1_PHYS_BASE (ORION_REGS_PHYS_BASE | 0xa0000) -#define ORION_USB1_VIRT_BASE (ORION_REGS_VIRT_BASE | 0xa0000) -#define ORION_USB1_REG(x) (ORION_USB1_VIRT_BASE | (x)) - -/******************************************************************************* - * Device Bus Registers - ******************************************************************************/ -#define MPP_0_7_CTRL ORION_DEV_BUS_REG(0x000) -#define MPP_8_15_CTRL ORION_DEV_BUS_REG(0x004) -#define MPP_16_19_CTRL ORION_DEV_BUS_REG(0x050) -#define MPP_DEV_CTRL ORION_DEV_BUS_REG(0x008) -#define MPP_RESET_SAMPLE ORION_DEV_BUS_REG(0x010) -#define GPIO_OUT ORION_DEV_BUS_REG(0x100) -#define GPIO_IO_CONF ORION_DEV_BUS_REG(0x104) -#define GPIO_BLINK_EN ORION_DEV_BUS_REG(0x108) -#define GPIO_IN_POL ORION_DEV_BUS_REG(0x10c) -#define GPIO_DATA_IN ORION_DEV_BUS_REG(0x110) -#define GPIO_EDGE_CAUSE ORION_DEV_BUS_REG(0x114) -#define GPIO_EDGE_MASK ORION_DEV_BUS_REG(0x118) -#define GPIO_LEVEL_MASK ORION_DEV_BUS_REG(0x11c) -#define DEV_BANK_0_PARAM ORION_DEV_BUS_REG(0x45c) -#define DEV_BANK_1_PARAM ORION_DEV_BUS_REG(0x460) -#define DEV_BANK_2_PARAM ORION_DEV_BUS_REG(0x464) -#define DEV_BANK_BOOT_PARAM ORION_DEV_BUS_REG(0x46c) -#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0) -#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0) -#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4) -#define GPIO_MAX 32 - -/*************************************************************************** - * Orion CPU Bridge Registers - **************************************************************************/ -#define CPU_CONF ORION_BRIDGE_REG(0x100) -#define CPU_CTRL ORION_BRIDGE_REG(0x104) -#define CPU_RESET_MASK ORION_BRIDGE_REG(0x108) -#define CPU_SOFT_RESET ORION_BRIDGE_REG(0x10c) -#define POWER_MNG_CTRL_REG ORION_BRIDGE_REG(0x11C) -#define BRIDGE_CAUSE ORION_BRIDGE_REG(0x110) -#define BRIDGE_MASK ORION_BRIDGE_REG(0x114) -#define BRIDGE_INT_TIMER0 0x0002 -#define BRIDGE_INT_TIMER1 0x0004 -#define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200) -#define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204) - - -#endif diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion5x/debug-macro.S similarity index 73% rename from include/asm-arm/arch-orion/debug-macro.S rename to include/asm-arm/arch-orion5x/debug-macro.S index c847f8c9250..4f98f3ba292 100644 --- a/include/asm-arm/arch-orion/debug-macro.S +++ b/include/asm-arm/arch-orion5x/debug-macro.S @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/debug-macro.S + * include/asm-arm/arch-orion5x/debug-macro.S * * Debugging macro include header * @@ -8,13 +8,13 @@ * published by the Free Software Foundation. */ -#include +#include .macro addruart,rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? - ldreq \rx, =ORION_REGS_PHYS_BASE - ldrne \rx, =ORION_REGS_VIRT_BASE + ldreq \rx, =ORION5X_REGS_PHYS_BASE + ldrne \rx, =ORION5X_REGS_VIRT_BASE orr \rx, \rx, #0x00012000 .endm diff --git a/include/asm-arm/arch-orion/dma.h b/include/asm-arm/arch-orion5x/dma.h similarity index 100% rename from include/asm-arm/arch-orion/dma.h rename to include/asm-arm/arch-orion5x/dma.h diff --git a/include/asm-arm/arch-orion/entry-macro.S b/include/asm-arm/arch-orion5x/entry-macro.S similarity index 90% rename from include/asm-arm/arch-orion/entry-macro.S rename to include/asm-arm/arch-orion5x/entry-macro.S index cda096b2acf..d8ef54c0ee9 100644 --- a/include/asm-arm/arch-orion/entry-macro.S +++ b/include/asm-arm/arch-orion5x/entry-macro.S @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/entry-macro.S + * include/asm-arm/arch-orion5x/entry-macro.S * * Low-level IRQ helper macros for Orion platforms * @@ -8,7 +8,7 @@ * warranty of any kind, whether express or implied. */ -#include +#include .macro disable_fiq .endm diff --git a/include/asm-arm/arch-orion/gpio.h b/include/asm-arm/arch-orion5x/gpio.h similarity index 79% rename from include/asm-arm/arch-orion/gpio.h rename to include/asm-arm/arch-orion5x/gpio.h index d66284f9a14..c85e498388b 100644 --- a/include/asm-arm/arch-orion/gpio.h +++ b/include/asm-arm/arch-orion5x/gpio.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/gpio.h + * include/asm-arm/arch-orion5x/gpio.h * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -12,17 +12,17 @@ extern int gpio_direction_input(unsigned pin); extern int gpio_direction_output(unsigned pin, int value); extern int gpio_get_value(unsigned pin); extern void gpio_set_value(unsigned pin, int value); -extern void orion_gpio_set_blink(unsigned pin, int blink); +extern void orion5x_gpio_set_blink(unsigned pin, int blink); extern void gpio_display(void); /* debug */ static inline int gpio_to_irq(int pin) { - return pin + IRQ_ORION_GPIO_START; + return pin + IRQ_ORION5X_GPIO_START; } static inline int irq_to_gpio(int irq) { - return irq - IRQ_ORION_GPIO_START; + return irq - IRQ_ORION5X_GPIO_START; } #include /* cansleep wrappers */ diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion5x/hardware.h similarity index 77% rename from include/asm-arm/arch-orion/hardware.h rename to include/asm-arm/arch-orion5x/hardware.h index 998af6029c7..5d2d8e0b563 100644 --- a/include/asm-arm/arch-orion/hardware.h +++ b/include/asm-arm/arch-orion5x/hardware.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/hardware.h + * include/asm-arm/arch-orion5x/hardware.h * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -9,13 +9,13 @@ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H -#include "orion.h" +#include "orion5x.h" #define pcibios_assign_all_busses() 1 #define PCIBIOS_MIN_IO 0x00001000 #define PCIBIOS_MIN_MEM 0x01000000 -#define PCIMEM_BASE ORION_PCIE_MEM_PHYS_BASE +#define PCIMEM_BASE ORION5X_PCIE_MEM_PHYS_BASE #endif diff --git a/include/asm-arm/arch-orion/io.h b/include/asm-arm/arch-orion5x/io.h similarity index 61% rename from include/asm-arm/arch-orion/io.h rename to include/asm-arm/arch-orion5x/io.h index 23820153b61..5148ab7ad1f 100644 --- a/include/asm-arm/arch-orion/io.h +++ b/include/asm-arm/arch-orion5x/io.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/io.h + * include/asm-arm/arch-orion5x/io.h * * Tzachi Perelstein * @@ -11,20 +11,20 @@ #ifndef __ASM_ARCH_IO_H #define __ASM_ARCH_IO_H -#include "orion.h" +#include "orion5x.h" #define IO_SPACE_LIMIT 0xffffffff -#define IO_SPACE_REMAP ORION_PCI_SYS_IO_BASE +#define IO_SPACE_REMAP ORION5X_PCI_SYS_IO_BASE static inline void __iomem * __arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) { void __iomem *retval; - if (mtype == MT_DEVICE && size && paddr >= ORION_REGS_PHYS_BASE && - paddr + size <= ORION_REGS_PHYS_BASE + ORION_REGS_SIZE) { - retval = (void __iomem *)ORION_REGS_VIRT_BASE + - (paddr - ORION_REGS_PHYS_BASE); + if (mtype == MT_DEVICE && size && paddr >= ORION5X_REGS_PHYS_BASE && + paddr + size <= ORION5X_REGS_PHYS_BASE + ORION5X_REGS_SIZE) { + retval = (void __iomem *)ORION5X_REGS_VIRT_BASE + + (paddr - ORION5X_REGS_PHYS_BASE); } else { retval = __arm_ioremap(paddr, size, mtype); } @@ -35,8 +35,8 @@ __arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) static inline void __arch_iounmap(void __iomem *addr) { - if (addr < (void __iomem *)ORION_REGS_VIRT_BASE || - addr >= (void __iomem *)(ORION_REGS_VIRT_BASE + ORION_REGS_SIZE)) + if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE || + addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE)) __iounmap(addr); } @@ -54,15 +54,15 @@ static inline void __iomem *__io(unsigned long addr) /***************************************************************************** * Helpers to access Orion registers ****************************************************************************/ -#define orion_read(r) __raw_readl(r) -#define orion_write(r, val) __raw_writel(val, r) +#define orion5x_read(r) __raw_readl(r) +#define orion5x_write(r, val) __raw_writel(val, r) /* * These are not preempt-safe. Locks, if needed, must be taken * care of by the caller. */ -#define orion_setbits(r, mask) orion_write((r), orion_read(r) | (mask)) -#define orion_clrbits(r, mask) orion_write((r), orion_read(r) & ~(mask)) +#define orion5x_setbits(r, mask) orion5x_write((r), orion5x_read(r) | (mask)) +#define orion5x_clrbits(r, mask) orion5x_write((r), orion5x_read(r) & ~(mask)) #endif diff --git a/include/asm-arm/arch-orion5x/irqs.h b/include/asm-arm/arch-orion5x/irqs.h new file mode 100644 index 00000000000..abdd61a4833 --- /dev/null +++ b/include/asm-arm/arch-orion5x/irqs.h @@ -0,0 +1,62 @@ +/* + * include/asm-arm/arch-orion5x/irqs.h + * + * IRQ definitions for Orion SoC + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +#include "orion5x.h" /* need GPIO_MAX */ + +/* + * Orion Main Interrupt Controller + */ +#define IRQ_ORION5X_BRIDGE 0 +#define IRQ_ORION5X_DOORBELL_H2C 1 +#define IRQ_ORION5X_DOORBELL_C2H 2 +#define IRQ_ORION5X_UART0 3 +#define IRQ_ORION5X_UART1 4 +#define IRQ_ORION5X_I2C 5 +#define IRQ_ORION5X_GPIO_0_7 6 +#define IRQ_ORION5X_GPIO_8_15 7 +#define IRQ_ORION5X_GPIO_16_23 8 +#define IRQ_ORION5X_GPIO_24_31 9 +#define IRQ_ORION5X_PCIE0_ERR 10 +#define IRQ_ORION5X_PCIE0_INT 11 +#define IRQ_ORION5X_USB1_CTRL 12 +#define IRQ_ORION5X_DEV_BUS_ERR 14 +#define IRQ_ORION5X_PCI_ERR 15 +#define IRQ_ORION5X_USB_BR_ERR 16 +#define IRQ_ORION5X_USB0_CTRL 17 +#define IRQ_ORION5X_ETH_RX 18 +#define IRQ_ORION5X_ETH_TX 19 +#define IRQ_ORION5X_ETH_MISC 20 +#define IRQ_ORION5X_ETH_SUM 21 +#define IRQ_ORION5X_ETH_ERR 22 +#define IRQ_ORION5X_IDMA_ERR 23 +#define IRQ_ORION5X_IDMA_0 24 +#define IRQ_ORION5X_IDMA_1 25 +#define IRQ_ORION5X_IDMA_2 26 +#define IRQ_ORION5X_IDMA_3 27 +#define IRQ_ORION5X_CESA 28 +#define IRQ_ORION5X_SATA 29 +#define IRQ_ORION5X_XOR0 30 +#define IRQ_ORION5X_XOR1 31 + +/* + * Orion General Purpose Pins + */ +#define IRQ_ORION5X_GPIO_START 32 +#define NR_GPIO_IRQS GPIO_MAX + +#define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) + + +#endif diff --git a/include/asm-arm/arch-orion/memory.h b/include/asm-arm/arch-orion5x/memory.h similarity index 85% rename from include/asm-arm/arch-orion/memory.h rename to include/asm-arm/arch-orion5x/memory.h index d9300d62a53..80053a7afc7 100644 --- a/include/asm-arm/arch-orion/memory.h +++ b/include/asm-arm/arch-orion5x/memory.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/memory.h + * include/asm-arm/arch-orion5x/memory.h * * Marvell Orion memory definitions */ diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h new file mode 100644 index 00000000000..206ddd71e19 --- /dev/null +++ b/include/asm-arm/arch-orion5x/orion5x.h @@ -0,0 +1,159 @@ +/* + * include/asm-arm/arch-orion5x/orion5x.h + * + * Generic definitions of Orion SoC flavors: + * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2. + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_ORION5X_H +#define __ASM_ARCH_ORION5X_H + +/***************************************************************************** + * Orion Address Maps + * + * phys + * e0000000 PCIe MEM space + * e8000000 PCI MEM space + * f0000000 PCIe WA space (Orion-1/Orion-NAS only) + * f1000000 on-chip peripheral registers + * f2000000 PCIe I/O space + * f2100000 PCI I/O space + * f4000000 device bus mappings (boot) + * fa000000 device bus mappings (cs0) + * fa800000 device bus mappings (cs2) + * fc000000 device bus mappings (cs0/cs1) + * + * virt phys size + * fdd00000 f1000000 1M on-chip peripheral registers + * fde00000 f2000000 1M PCIe I/O space + * fdf00000 f2100000 1M PCI I/O space + * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) + ****************************************************************************/ +#define ORION5X_REGS_PHYS_BASE 0xf1000000 +#define ORION5X_REGS_VIRT_BASE 0xfdd00000 +#define ORION5X_REGS_SIZE SZ_1M + +#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 +#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000 +#define ORION5X_PCIE_IO_BUS_BASE 0x00000000 +#define ORION5X_PCIE_IO_SIZE SZ_1M + +#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 +#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000 +#define ORION5X_PCI_IO_BUS_BASE 0x00100000 +#define ORION5X_PCI_IO_SIZE SZ_1M + +/* Relevant only for Orion-1/Orion-NAS */ +#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 +#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 +#define ORION5X_PCIE_WA_SIZE SZ_16M + +#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 +#define ORION5X_PCIE_MEM_SIZE SZ_128M + +#define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000 +#define ORION5X_PCI_MEM_SIZE SZ_128M + +/******************************************************************************* + * Supported Devices & Revisions + ******************************************************************************/ +/* Orion-1 (88F5181) */ +#define MV88F5181_DEV_ID 0x5181 +#define MV88F5181_REV_B1 3 +/* Orion-NAS (88F5182) */ +#define MV88F5182_DEV_ID 0x5182 +#define MV88F5182_REV_A2 2 +/* Orion-2 (88F5281) */ +#define MV88F5281_DEV_ID 0x5281 +#define MV88F5281_REV_D1 5 +#define MV88F5281_REV_D2 6 + +/******************************************************************************* + * Orion Registers Map + ******************************************************************************/ +#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) +#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x)) + +#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) +#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) +#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) +#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000) +#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000) +#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000) +#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100) +#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100) + +#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000) +#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x)) +#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) + +#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000) +#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) + +#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000) +#define ORION5X_PCIE_REG(x) (ORION5X_PCIE_VIRT_BASE | (x)) + +#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000) +#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000) +#define ORION5X_USB0_REG(x) (ORION5X_USB0_VIRT_BASE | (x)) + +#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000) +#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000) +#define ORION5X_ETH_REG(x) (ORION5X_ETH_VIRT_BASE | (x)) + +#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) +#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) +#define ORION5X_SATA_REG(x) (ORION5X_SATA_VIRT_BASE | (x)) + +#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) +#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) +#define ORION5X_USB1_REG(x) (ORION5X_USB1_VIRT_BASE | (x)) + +/******************************************************************************* + * Device Bus Registers + ******************************************************************************/ +#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000) +#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004) +#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050) +#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008) +#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010) +#define GPIO_OUT ORION5X_DEV_BUS_REG(0x100) +#define GPIO_IO_CONF ORION5X_DEV_BUS_REG(0x104) +#define GPIO_BLINK_EN ORION5X_DEV_BUS_REG(0x108) +#define GPIO_IN_POL ORION5X_DEV_BUS_REG(0x10c) +#define GPIO_DATA_IN ORION5X_DEV_BUS_REG(0x110) +#define GPIO_EDGE_CAUSE ORION5X_DEV_BUS_REG(0x114) +#define GPIO_EDGE_MASK ORION5X_DEV_BUS_REG(0x118) +#define GPIO_LEVEL_MASK ORION5X_DEV_BUS_REG(0x11c) +#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c) +#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460) +#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464) +#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c) +#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0) +#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) +#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) +#define GPIO_MAX 32 + +/*************************************************************************** + * Orion CPU Bridge Registers + **************************************************************************/ +#define CPU_CONF ORION5X_BRIDGE_REG(0x100) +#define CPU_CTRL ORION5X_BRIDGE_REG(0x104) +#define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108) +#define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c) +#define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C) +#define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110) +#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) +#define BRIDGE_INT_TIMER0 0x0002 +#define BRIDGE_INT_TIMER1 0x0004 +#define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200) +#define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204) + + +#endif diff --git a/include/asm-arm/arch-orion/system.h b/include/asm-arm/arch-orion5x/system.h similarity index 76% rename from include/asm-arm/arch-orion/system.h rename to include/asm-arm/arch-orion5x/system.h index 653f992bbe6..3f1d1e2d38f 100644 --- a/include/asm-arm/arch-orion/system.h +++ b/include/asm-arm/arch-orion5x/system.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/system.h + * include/asm-arm/arch-orion5x/system.h * * Tzachi Perelstein * @@ -12,7 +12,7 @@ #define __ASM_ARCH_SYSTEM_H #include -#include +#include static inline void arch_idle(void) { @@ -24,8 +24,8 @@ static inline void arch_reset(char mode) /* * Enable and issue soft reset */ - orion_setbits(CPU_RESET_MASK, (1 << 2)); - orion_setbits(CPU_SOFT_RESET, 1); + orion5x_setbits(CPU_RESET_MASK, (1 << 2)); + orion5x_setbits(CPU_SOFT_RESET, 1); } diff --git a/include/asm-arm/arch-orion/timex.h b/include/asm-arm/arch-orion5x/timex.h similarity index 79% rename from include/asm-arm/arch-orion/timex.h rename to include/asm-arm/arch-orion5x/timex.h index 85588d9c22e..31c568e28cc 100644 --- a/include/asm-arm/arch-orion/timex.h +++ b/include/asm-arm/arch-orion5x/timex.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/timex.h + * include/asm-arm/arch-orion5x/timex.h * * Tzachi Perelstein * @@ -10,4 +10,4 @@ #define CLOCK_TICK_RATE (100 * HZ) -#define ORION_TCLK 166666667 +#define ORION5X_TCLK 166666667 diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion5x/uncompress.h similarity index 89% rename from include/asm-arm/arch-orion/uncompress.h rename to include/asm-arm/arch-orion5x/uncompress.h index 03306cdd51b..5c13d4fafb4 100644 --- a/include/asm-arm/arch-orion/uncompress.h +++ b/include/asm-arm/arch-orion5x/uncompress.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/uncompress.h + * include/asm-arm/arch-orion5x/uncompress.h * * Tzachi Perelstein * @@ -8,7 +8,7 @@ * warranty of any kind, whether express or implied. */ -#include +#include #define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0)) #define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14)) diff --git a/include/asm-arm/arch-orion/vmalloc.h b/include/asm-arm/arch-orion5x/vmalloc.h similarity index 51% rename from include/asm-arm/arch-orion/vmalloc.h rename to include/asm-arm/arch-orion5x/vmalloc.h index 9d580278d2b..2b3061e90dc 100644 --- a/include/asm-arm/arch-orion/vmalloc.h +++ b/include/asm-arm/arch-orion5x/vmalloc.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/vmalloc.h + * include/asm-arm/arch-orion5x/vmalloc.h */ #define VMALLOC_END 0xfd800000 -- GitLab From 3ad0920d7b11a88379ec4db186be3eee667c4278 Mon Sep 17 00:00:00 2001 From: Steve Birtles Date: Sat, 9 Feb 2008 04:49:55 +0100 Subject: [PATCH 026/212] [ARM] 4825/1: adds support for YL9200 board 1. Configuration file for YL9200 2. Board file fro YL9200 Adds support for the UCdragon YL9200 board available widly in China Signed-off-by: steve birtles Signed-off-by: Russell King --- arch/arm/configs/yl9200_defconfig | 1216 ++++++++++++++++++++++++++++ arch/arm/mach-at91/board-yl-9200.c | 683 ++++++++++++++++ 2 files changed, 1899 insertions(+) create mode 100644 arch/arm/configs/yl9200_defconfig create mode 100755 arch/arm/mach-at91/board-yl-9200.c diff --git a/arch/arm/configs/yl9200_defconfig b/arch/arm/configs/yl9200_defconfig new file mode 100644 index 00000000000..26de37f7468 --- /dev/null +++ b/arch/arm/configs/yl9200_defconfig @@ -0,0 +1,1216 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.24-rc6 +# Fri Jan 11 09:53:59 2008 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FAIR_USER_SCHED=y +# CONFIG_FAIR_CGROUP_SCHED is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +CONFIG_ARCH_AT91=y +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set + +# +# Boot options +# + +# +# Power management +# + +# +# Atmel AT91 System-on-Chip +# +CONFIG_ARCH_AT91RM9200=y +# CONFIG_ARCH_AT91SAM9260 is not set +# CONFIG_ARCH_AT91SAM9261 is not set +# CONFIG_ARCH_AT91SAM9263 is not set +# CONFIG_ARCH_AT91SAM9RL is not set +# CONFIG_ARCH_AT91X40 is not set +CONFIG_AT91_PMC_UNIT=y + +# +# AT91RM9200 Board Type +# +# CONFIG_MACH_ONEARM is not set +CONFIG_ARCH_AT91RM9200DK=y +# CONFIG_MACH_AT91RM9200EK is not set +# CONFIG_MACH_CSB337 is not set +# CONFIG_MACH_CSB637 is not set +# CONFIG_MACH_CARMEVA is not set +# CONFIG_MACH_ATEB9200 is not set +# CONFIG_MACH_KB9200 is not set +# CONFIG_MACH_PICOTUX2XX is not set +# CONFIG_MACH_KAFA is not set +CONFIG_MACH_YL9200=y + +# +# AT91 Board Options +# +# CONFIG_MTD_AT91_DATAFLASH_CARD is not set + +# +# AT91 Feature Selections +# +# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM920T=y +CONFIG_CPU_32v4T=y +CONFIG_CPU_ABRT_EV4T=y +CONFIG_CPU_CACHE_V4WT=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_THUMB is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_HZ=100 +# CONFIG_AEABI is not set +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw" +# CONFIG_XIP_KERNEL is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set +# CONFIG_ARTHUR is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_SUSPEND_UP_POSSIBLE=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_RAM=y +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x0000000 +CONFIG_MTD_PHYSMAP_LEN=0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +CONFIG_MTD_PLATRAM=y + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_AT91=y +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=3 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MISC_DEVICES is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +CONFIG_DAVICOM_PHY=y +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_ARM_AT91_ETHER=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=640 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=y +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_UCB1400 is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +# CONFIG_SERIAL_ATMEL_TTYAT is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CHARDEV is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +CONFIG_SPI=y +CONFIG_SPI_DEBUG=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_ATMEL=y + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_S1D135XX=y +# CONFIG_FB_VIRTUAL is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_LTV350QV is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_CORGI is not set + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=y + +# +# Display hardware drivers +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_DEBUG=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_USB_HIDDEV is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +CONFIG_USB_DEBUG=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MICROTEK is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +CONFIG_USB_GADGET_M66592=y +CONFIG_USB_M66592=y +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=y +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +CONFIG_MMC=y +CONFIG_MMC_DEBUG=y +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +# CONFIG_SDIO_UART is not set + +# +# MMC/SD Host Controller Drivers +# +CONFIG_MMC_AT91=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +CONFIG_LEDS_GPIO=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_AT91RM9200=y + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=y +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=y +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set + +# +# Miscellaneous filesystems +# +# CONFIG_HFSPLUS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=1 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +CONFIG_INSTRUMENTATION=y +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENABLE_MUST_CHECK is not set +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +CONFIG_SLUB_DEBUG_ON=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_DEBUG_KOBJECT=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +CONFIG_DEBUG_LIST=y +# CONFIG_DEBUG_SG is not set +CONFIG_FRAME_POINTER=y +CONFIG_FORCED_INLINING=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SAMPLES is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c new file mode 100755 index 00000000000..b5717108991 --- /dev/null +++ b/arch/arm/mach-at91/board-yl-9200.c @@ -0,0 +1,683 @@ +/* + * linux/arch/arm/mach-at91/board-yl-9200.c + * + * Adapted from: + *various board files in + * /arch/arm/mach-at91 + * modifications to convert to YL-9200 platform + * Copyright (C) 2007 S.Birtles + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +/*#include */ +#include +#include + +/*#include */ +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "generic.h" +#include + +#define YL_9200_FLASH_BASE AT91_CHIPSELECT_0 +#define YL_9200_FLASH_SIZE 0x800000 + +/* + * Serial port configuration. + * 0 .. 3 = USART0 .. USART3 + * 4 = DBGU + *atmel_usart.0: ttyS0 at MMIO 0xfefff200 (irq = 1) is a ATMEL_SERIAL + *atmel_usart.1: ttyS1 at MMIO 0xfffc0000 (irq = 6) is a ATMEL_SERIAL + *atmel_usart.2: ttyS2 at MMIO 0xfffc4000 (irq = 7) is a ATMEL_SERIAL + *atmel_usart.3: ttyS3 at MMIO 0xfffc8000 (irq = 8) is a ATMEL_SERIAL + *atmel_usart.4: ttyS4 at MMIO 0xfffcc000 (irq = 9) is a ATMEL_SERIAL + * on the YL-9200 we are sitting at the following + *ttyS0 at MMIO 0xfefff200 (irq = 1) is a AT91_SERIAL + *ttyS1 at MMIO 0xfefc4000 (irq = 7) is a AT91_SERIAL + */ + +/* extern void __init yl_9200_add_device_sounder(struct gpio_sounder *sounders, int nr);*/ + +static struct at91_uart_config __initdata yl_9200_uart_config = { + .console_tty = 0, /* ttyS0 */ + .nr_tty = 3, + .tty_map = { 4, 1, 0, -1, -1 } /* ttyS0, ..., ttyS4 */ +}; + +static void __init yl_9200_map_io(void) +{ + /* Initialize processor: 18.432 MHz crystal */ + /*Also initialises register clocks & gpio*/ + at91rm9200_initialize(18432000, AT91RM9200_PQFP); /*we have a 3 bank system*/ + + /* Setup the serial ports and console */ + at91_init_serial(&yl_9200_uart_config); + + /* Setup the LEDs D2=PB17,D3=PB16 */ + at91_init_leds(AT91_PIN_PB16,AT91_PIN_PB17); /*cpu-led,timer-led*/ +} + +static void __init yl_9200_init_irq(void) +{ + at91rm9200_init_interrupts(NULL); +} + +static struct at91_eth_data __initdata yl_9200_eth_data = { + .phy_irq_pin = AT91_PIN_PB28, + .is_rmii = 1, +}; + +static struct at91_usbh_data __initdata yl_9200_usbh_data = { + .ports = 1, /* this should be 1 not 2 for the Yl9200*/ +}; + +static struct at91_udc_data __initdata yl_9200_udc_data = { +/*on sheet 7 Schemitic rev 1.0*/ + .pullup_pin = AT91_PIN_PC4, + .vbus_pin= AT91_PIN_PC5, + .pullup_active_low = 1, /*ACTIVE LOW!! due to PNP transistor on page 7*/ + +}; +/* +static struct at91_cf_data __initdata yl_9200_cf_data = { +TODO S.BIRTLES + .det_pin = AT91_PIN_xxx, + .rst_pin = AT91_PIN_xxx, + .irq_pin = ... not connected + .vcc_pin = ... always powered + +}; +*/ +static struct at91_mmc_data __initdata yl_9200_mmc_data = { + .det_pin = AT91_PIN_PB9, /*THIS LOOKS CORRECT SHEET7*/ +/* .wp_pin = ... not connected SHEET7*/ + .slot_b = 0, + .wire4 = 1, + +}; + +/* -------------------------------------------------------------------- + * Touch screen + * -------------------------------------------------------------------- */ +#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) +static int ads7843_pendown_state(void) +{ + return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */ +} + +static void __init at91_init_device_ts(void) +{ +/*IMPORTANT NOTE THE SPI INTERFACE IS ALREADY CONFIGURED BY XXX_DEVICES.C +THAT IS TO SAY THAT MISO,MOSI,SPCK AND CS are already configured +we only need to enable the other datapins which are: +PB10/RK1 BUSY +*/ +/* Touchscreen BUSY signal , pin,use pullup ( TODO not currently used in the ADS7843/6.c driver)*/ +at91_set_gpio_input(AT91_PIN_PB10, 1); +} + +#else +static void __init at91_init_device_ts(void) {} +#endif + +static struct ads7846_platform_data ads_info = { + .model = 7843, + .x_min = 150, + .x_max = 3830, + .y_min = 190, + .y_max = 3830, + .vref_delay_usecs = 100, +/* for a 8" touch screen*/ + //.x_plate_ohms = 603, //= 450, S.Birtles TODO + //.y_plate_ohms = 332, //= 250, S.Birtles TODO +/*for a 10.4" touch screen*/ + //.x_plate_ohms =611, + //.y_plate_ohms =325, + + .x_plate_ohms = 576, + .y_plate_ohms = 366, + // + .pressure_max = 15000, /*generally nonsense on the 7843*/ + /*number of times to send query to chip in a given run 0 equals one time (do not set to 0!! ,there is a bug in ADS 7846 code)*/ + .debounce_max = 1, + .debounce_rep = 0, + .debounce_tol = (~0), + .get_pendown_state = ads7843_pendown_state, +}; + +/*static struct canbus_platform_data can_info = { + .model = 2510, +}; +*/ + +static struct spi_board_info yl_9200_spi_devices[] = { +/*this sticks it at: + /sys/devices/platform/atmel_spi.0/spi0.0 + /sys/bus/platform/devices/ +Documentation/spi IIRC*/ + +#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) + /*(this IS correct 04-NOV-2007)*/ + { + .modalias = "ads7846", /* because the driver is called ads7846*/ + .chip_select = 0, /*THIS MUST BE AN INDEX INTO AN ARRAY OF pins */ +/*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select*/ + /*.controller_data =AT91_PIN_PA3 ,*/ + .max_speed_hz = 5000*26, /*(4700 * 26)-125000 * 26, (max sample rate @ 3V) * (cmd + data + overhead) */ + .bus_num = 0, + .platform_data = &ads_info, + .irq = AT91_PIN_PB11, + }, +#endif +/*we need to put our CAN driver data here!!*/ +/*THIS IS ALL DUMMY DATA*/ +/* { + .modalias = "mcp2510", //DUMMY for MCP2510 chip + .chip_select = 1,*/ /*THIS MUST BE AN INDEX INTO AN ARRAY OF pins */ + /*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select */ + /* .controller_data =AT91_PIN_PA4 , + .max_speed_hz = 25000 * 26, + .bus_num = 0, + .platform_data = &can_info, + .irq = AT91_PIN_PC0, + }, + */ + //max SPI chip needs to go here +}; + +static struct mtd_partition __initdata yl_9200_nand_partition[] = { + { + .name = "AT91 NAND partition 1, boot", + .offset = 0, + .size = 1 * SZ_256K + }, + { + .name = "AT91 NAND partition 2, kernel", + .offset = 1 * SZ_256K, + .size = 2 * SZ_1M - 1 * SZ_256K + }, + { + .name = "AT91 NAND partition 3, filesystem", + .offset = 2 * SZ_1M, + .size = 14 * SZ_1M + }, + { + .name = "AT91 NAND partition 4, storage", + .offset = 16 * SZ_1M, + .size = 16 * SZ_1M + }, + { + .name = "AT91 NAND partition 5, ext-fs", + .offset = 32 * SZ_1M, + .size = 32 * SZ_1M + }, +}; + +static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) +{ + *num_partitions = ARRAY_SIZE(yl_9200_nand_partition); + return yl_9200_nand_partition; +} + +static struct at91_nand_data __initdata yl_9200_nand_data = { + .ale= 6, + .cle= 7, + /*.det_pin = AT91_PIN_PCxx,*/ /*we don't have a det pin because NandFlash is fixed to board*/ + .rdy_pin = AT91_PIN_PC14, /*R/!B Sheet10*/ + .enable_pin = AT91_PIN_PC15, /*!CE Sheet10 */ + .partition_info = nand_partitions, +}; + + + +/* +TODO S.Birtles +potentially a problem with the size above +physmap platform flash device: 00800000 at 10000000 +physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank +NOR chip too large to fit in mapping. Attempting to cope... + Intel/Sharp Extended Query Table at 0x0031 +Using buffer write method +cfi_cmdset_0001: Erase suspend on write enabled +Reducing visibility of 16384KiB chip to 8192KiB +*/ + +static struct mtd_partition yl_9200_flash_partitions[] = { + { + .name = "Bootloader", + .size = 0x00040000, + .offset = 0, + .mask_flags = MTD_WRITEABLE /* force read-only */ + },{ + .name = "Kernel", + .size = 0x001C0000, + .offset = 0x00040000, + },{ + .name = "Filesystem", + .size = MTDPART_SIZ_FULL, + .offset = 0x00200000 + } + +}; + +static struct physmap_flash_data yl_9200_flash_data = { + .width = 2, + .parts = yl_9200_flash_partitions, + .nr_parts = ARRAY_SIZE(yl_9200_flash_partitions), +}; + +static struct resource yl_9200_flash_resources[] = { +{ + .start = YL_9200_FLASH_BASE, + .end = YL_9200_FLASH_BASE + YL_9200_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device yl_9200_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &yl_9200_flash_data, + }, + .resource = yl_9200_flash_resources, + .num_resources = ARRAY_SIZE(yl_9200_flash_resources), +}; + + +static struct gpio_led yl_9200_leds[] = { +/*D2 &D3 are passed directly in via at91_init_leds*/ + { + .name = "led4", /*D4*/ + .gpio = AT91_PIN_PB15, + .active_low = 1, + .default_trigger = "heartbeat", + /*.default_trigger = "timer",*/ + }, + { + .name = "led5", /*D5*/ + .gpio = AT91_PIN_PB8, + .active_low = 1, + .default_trigger = "heartbeat", + } +}; + +//static struct gpio_sounder yl_9200_sounder[] = {*/ +/*This is a simple speaker attached to a gpo line*/ + +// { +// .name = "Speaker", /*LS1*/ +// .gpio = AT91_PIN_PA22, +// .active_low = 0, +// .default_trigger = "heartbeat", + /*.default_trigger = "timer",*/ +// }, +//}; + + + +static struct i2c_board_info __initdata yl_9200_i2c_devices[] = { + { + /*TODO*/ + I2C_BOARD_INFO("CS4334", 0x00), + } +}; + + + /* + * GPIO Buttons + */ +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +static struct gpio_keys_button yl_9200_buttons[] = { + { + .gpio = AT91_PIN_PA24, + .code = BTN_2, + .desc = "SW2", + .active_low = 1, + .wakeup = 1, + }, + { + .gpio = AT91_PIN_PB1, + .code = BTN_3, + .desc = "SW3", + .active_low = 1, + .wakeup = 1, + }, + { + .gpio = AT91_PIN_PB2, + .code = BTN_4, + .desc = "SW4", + .active_low = 1, + .wakeup = 1, + }, + { + .gpio = AT91_PIN_PB6, + .code = BTN_5, + .desc = "SW5", + .active_low = 1, + .wakeup = 1, + }, + +}; + +static struct gpio_keys_platform_data yl_9200_button_data = { + .buttons = yl_9200_buttons, + .nbuttons = ARRAY_SIZE(yl_9200_buttons), +}; + +static struct platform_device yl_9200_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &yl_9200_button_data, + } +}; + +static void __init yl_9200_add_device_buttons(void) +{ + //SW2 + at91_set_gpio_input(AT91_PIN_PA24, 0); + at91_set_deglitch(AT91_PIN_PA24, 1); + + //SW3 + at91_set_gpio_input(AT91_PIN_PB1, 0); + at91_set_deglitch(AT91_PIN_PB1, 1); + //SW4 + at91_set_gpio_input(AT91_PIN_PB2, 0); + at91_set_deglitch(AT91_PIN_PB2, 1); + + //SW5 + at91_set_gpio_input(AT91_PIN_PB6, 0); + at91_set_deglitch(AT91_PIN_PB6, 1); + + + at91_set_gpio_output(AT91_PIN_PB7, 1); /* #TURN BUTTONS ON, SHEET 5 of schematics */ + platform_device_register(&yl_9200_button_device); +} +#else +static void __init yl_9200_add_device_buttons(void) {} +#endif + +#if defined(CONFIG_FB_S1D135XX) || defined(CONFIG_FB_S1D13XXX_MODULE) +#include